基于單片機(jī)的步進(jìn)電機(jī)電路控制外文翻譯

1、淮 陰 工 學(xué) 院畢業(yè)設(shè)計(jì)(論文)外文翻譯學(xué) 生 姓 名：趙 輝學(xué) 號：專 業(yè)：電子信息工程設(shè)計(jì)(論文)題目：基于單片機(jī)的步進(jìn)電機(jī)控制電路設(shè)計(jì)指 導(dǎo) 教 師:莊 立 運(yùn) 2012年 4 月 10日基于單片機(jī)的步進(jìn)電機(jī)電路控制設(shè)計(jì) 89C51是一種帶4K字節(jié)閃爍可編程可擦除只讀存儲器（FPEROMFalsh Programmable and Erasable Read Only Memory）的低電壓、高性能CMOS8位微處理器，俗稱單片機(jī)。該器件采用ATMEL高密度非易失存儲器制造技術(shù)制造，與工業(yè)標(biāo)準(zhǔn)的MCS-51指令集和輸出管腳相兼容。由于將多功能8位CPU和閃爍存儲器組合在單個芯片中，AT

2、MEL的89C51是一種高效微控制器，89C2051是它的一種精簡版本。89C單片機(jī)為很多嵌入式控制系統(tǒng)提供了一種靈活性高且價廉的方案。功能特點(diǎn)與MCS-51 兼容 4K字節(jié)可編程閃爍存儲器 壽命：1000寫/擦循環(huán) 數(shù)據(jù)保留時間：10年 全靜態(tài)工作：0Hz-24MHz 三級程序存儲器鎖定 128*8位內(nèi)部RAM 32可編程I/O線 兩個16位定時器/計(jì)數(shù)器 5個中斷源 可編程串行通道 低功耗的閑置和掉電模式 片內(nèi)振蕩器和時鐘電路管腳說明VCC：供電電壓。 GND：接地。 P0口：P0口為一個8位漏級開路雙向I/O口，每腳可吸收8TTL門電流。當(dāng)P1口的管腳第一次寫1時，被定義為高阻輸入。P0

3、能夠用于外部程序數(shù)據(jù)存儲器，它可以被定義為數(shù)據(jù)/地址的低八位。在FIASH編程時，P0 口作為原碼輸入口，當(dāng)FIASH進(jìn)行校驗(yàn)時，P0輸出原碼，此時P0外部必須被拉高。 P1口：P1口是一個內(nèi)部提供上拉電阻的8位雙向I/O口，P1口緩沖器能接收輸出4TTL門電流。P1口管腳寫入1后，被內(nèi)部上拉為高，可用作輸入，P1口被外部下拉為低電平時，將輸出電流，這是由于內(nèi)部上拉的緣故。在FLASH編程和校驗(yàn)時，P1口作為第八位地址接收。 P2口：P2口為一個內(nèi)部上拉電阻的8位雙向I/O口，P2口緩沖器可接收，輸出4個TTL門電流，當(dāng)P2口被寫“1”時，其管腳被內(nèi)部上拉電阻拉高，且作為輸入。并因此作為輸入時

4、，P2口的管腳被外部拉低，將輸出電流。這是由于內(nèi)部上拉的緣故。P2口當(dāng)用于外部程序存儲器或16位地址外部數(shù)據(jù)存儲器進(jìn)行存取時，P2口輸出地址的高八位。在給出地址“1”時，它利用內(nèi)部上拉優(yōu)勢，當(dāng)對外部八位地址數(shù)據(jù)存儲器進(jìn)行讀寫時，P2口輸出其特殊功能寄存器的內(nèi)容。P2口在FLASH編程和校驗(yàn)時接收高八位地址信號和控制信號。 P3口：P3口管腳是8個帶內(nèi)部上拉電阻的雙向I/O口，可接收輸出4個TTL門電流。當(dāng)P3口寫入“1”后，它們被內(nèi)部上拉為高電平，并用作輸入。作為輸入，由于外部下拉為低電平，P3口將輸出電流（ILL）這是由于上拉的緣故。P3口也可作為AT89C51的一些特殊功能口. 口管腳 備

5、選功能 P3.0 RXD（串行輸入口） P3.1 TXD（串行輸出口） P3.2 /INT0（外部中斷0） P3.3 /INT1（外部中斷1） P3.4 T0（記時器0外部輸入） P3.5 T1（記時器1外部輸入） P3.6 /WR（外部數(shù)據(jù)存儲器寫選通） P3.7 /RD（外部數(shù)據(jù)存儲器讀選通） P3口同時為閃爍編程和編程校驗(yàn)接收一些控制信號。 RST：復(fù)位輸入。當(dāng)振蕩器復(fù)位器件時，要保持RST腳兩個機(jī)器周期的高電平時間。ALE/PROG：當(dāng)訪問外部存儲器時，地址鎖存允許的輸出電平用于鎖存地址的地位字節(jié)。在FLASH編程期間，此引腳用于輸入編程脈沖。在平時，ALE端以不變的頻率周期輸出正脈沖

6、信號，此頻率為振蕩器頻率的1/6。因此它可用作對外部輸出的脈沖或用于定時目的。然而要注意的是：每當(dāng)用作外部數(shù)據(jù)存儲器時，將跳過一個ALE脈沖。如想禁止ALE的輸出可在SFR8EH地址上置0。此時， ALE只有在執(zhí)行MOVX，MOVC指令是ALE才起作用。另外，該引腳被略微拉高。如果微處理器在外部執(zhí)行狀態(tài)ALE禁止，置位無效。 /PSEN：外部程序存儲器的選通信號。在由外部程序存儲器取指期間，每個機(jī)器周期兩次/PSEN有效。但在訪問外部數(shù)據(jù)存儲器時，這兩次有效的/PSEN信號將不出現(xiàn)。 /EA/VPP：當(dāng)/EA保持低電平時，則在此期間外部程序存儲器（0000H-FFFFH），不管是否有內(nèi)部程序存

7、儲器。注意加密方式1時，/EA將內(nèi)部鎖定為RESET；當(dāng)/EA端保持高電平時，此間內(nèi)部程序存儲器。在FLASH編程期間，此引腳也用于施加12V編程電源（VPP）。 XTAL1：反向振蕩放大器的輸入及內(nèi)部時鐘工作電路的輸入。 XTAL2：來自反向振蕩器的輸出。振蕩器特性XTAL1和XTAL2分別為反向放大器的輸入和輸出。該反向放大器可以配置為片內(nèi)振蕩器。石晶振蕩和陶瓷振蕩均可采用。如采用外部時鐘源驅(qū)動器件，XTAL2應(yīng)不接。由于輸入至內(nèi)部時鐘信號要通過一個二分頻觸發(fā)器，因此對外部時鐘信號的脈寬無任何要求，但必須保證脈沖的高低電平要求的寬度。Figure 1. Oscillator Connect

8、ions Figure 2. External Clock Drive芯片擦除整個PEROM陣列和三個鎖定位的電擦除可通過正確的控制信號組合，并保持ALE管腳處于低電平10ms 來完成。在芯片擦操作中，代碼陣列全被寫“1”且在任何非空存儲字節(jié)被重復(fù)編程以前，該操作必須被執(zhí)行。 此外，AT89C51設(shè)有穩(wěn)態(tài)邏輯，可以在低到零頻率的條件下靜態(tài)邏輯，支持兩種軟件可選的掉電模式。在閑置模式下，CPU停止工作。但RAM，定時器，計(jì)數(shù)器，串口和中斷系統(tǒng)仍在工作。在掉電模式下，保存RAM的內(nèi)容并且凍結(jié)振蕩器，禁止所用其他芯片功能，直到下一個硬件復(fù)位為止。空閑模式在空閑模式下,中央處理器把自己睡;所有的微外設(shè)

9、保持活躍。該模式調(diào)用的軟件。片上的內(nèi)容的公綿羊、所有的特殊功能寄存器不變在這個模式下?？臻e模式可以終止任何使中斷或由硬件復(fù)位。應(yīng)該指出的是,閑時終止一個硬件復(fù)位,設(shè)備通常程序執(zhí)行,從簡歷在它停止兩封,機(jī)器周期之前,內(nèi)部重置算法以控制。樣品的硬件抑制進(jìn)入內(nèi)部RAM在這種情況下,但進(jìn)入港口大頭針空洞。消除這種可能性一個出乎意料的寫信給一個港口銷閑時被終止,由復(fù)位、指導(dǎo)證明那個中調(diào)用一個空閑不應(yīng)該寫端口銷或外部存儲器。Power-down模式在power-down模式下,振子是結(jié)束了,但這個指令;用它召喚“power-down是最后的指令執(zhí)行。這片上的公綿羊、特殊功能寄存器值,直到power-dow

10、n保留自己的方式終止。唯一的退出,是一家五金power-down重置。SFRs重置重新定義,但不改變樣品的公羊。重置不應(yīng)該被激活之前VCC回到正常操作水平,都必須保持活躍的時間還不夠久,允許振蕩器來重新啟動和穩(wěn)定。程序記憶鎖位在芯片上的三個鎖位可以離開unprogrammed(U)或可編程(P)獲得的額外功能列在下表。當(dāng)鎖點(diǎn),1是程序邏輯電平EA銷樣品并就搭在重置。如果這個裝置是開機(jī)沒有重置,門閂初始化一個隨機(jī)值,認(rèn)為直到重置價值被激活。加入是必要的值EA是一致的邏輯與當(dāng)前水平銷為設(shè)備正常運(yùn)作步進(jìn)電機(jī)介紹步進(jìn)電機(jī)是將數(shù)字脈沖輸入轉(zhuǎn)換為模擬角度輸出的電磁增量運(yùn)動裝置。其內(nèi)在的步進(jìn)能力允許沒有反饋

11、的精確位置控制。 也就是說，他們可以在開環(huán)模式下跟蹤任何步階位置，因此執(zhí)行位置控制是不需要任何反饋的。步進(jìn)電機(jī)提供比直流電機(jī)每單位更高的峰值扭矩;此外，它們是無電刷電機(jī)，因此需要較少的維護(hù)。所有這些特性使得步進(jìn)電機(jī)在許多位置和速度控制系統(tǒng)的選擇中非常具有吸引力，例如如在計(jì)算機(jī)硬盤驅(qū)動器和打印機(jī)，代理表，機(jī)器人中的應(yīng)用等.盡管步進(jìn)電機(jī)有許多突出的特性，他們?nèi)栽馐苷袷幓虿环€(wěn)定現(xiàn)象。這種現(xiàn)象嚴(yán)重地限制其開環(huán)的動態(tài)性能和需要高速運(yùn)作的適用領(lǐng)域。 這種振蕩通常在步進(jìn)率低于1000脈沖/秒的時候發(fā)生，并已被確認(rèn)為中頻不穩(wěn)定或局部不穩(wěn)定1，或者動態(tài)不穩(wěn)定2。此外，步進(jìn)電機(jī)還有另一種不穩(wěn)定現(xiàn)象，也就是在步進(jìn)率

12、較高時，即使負(fù)荷扭矩小于其牽出扭矩，電動機(jī)也常常不同步。該文中將這種現(xiàn)象確定為高頻不穩(wěn)定性，因?yàn)樗员仍谥蓄l振蕩現(xiàn)象中發(fā)生的頻率更高的頻率出現(xiàn)。高頻不穩(wěn)定性不像中頻不穩(wěn)定性那樣被廣泛接受，而且還沒有一個方法來評估它。中頻振蕩已經(jīng)被廣泛地認(rèn)識了很長一段時間，但是，一個完整的了解還沒有牢固確立。這可以歸因于支配振蕩現(xiàn)象的非線性是相當(dāng)困難處理的。大多數(shù)研究人員在線性模型基礎(chǔ)上分析它1。盡管在許多情況下，這種處理方法是有效的或有益的，但為了更好地描述這一復(fù)雜的現(xiàn)象，在非線性理論基礎(chǔ)上的處理方法也是需要的。例如，基于線性模型只能看到電動機(jī)在某些供應(yīng)頻率下轉(zhuǎn)向局部不穩(wěn)定，并不能使被觀測的振蕩現(xiàn)象更多深入。

13、事實(shí)上，除非有人利用非線性理論，否則振蕩不能評估。窗體頂端窗體底端因此，在非線性動力學(xué)上利用被發(fā)展的數(shù)學(xué)理論處理振蕩或不穩(wěn)定是很重要的。值得指出的是，Taft和Gauthier3，還有Taft和Harned4使用的諸如在振蕩和不穩(wěn)定現(xiàn)象的分析中的極限環(huán)和分界線之類的數(shù)學(xué)概念，并取得了關(guān)于所謂非同步現(xiàn)象的一些非常有啟發(fā)性的見解。盡管如此，在這項(xiàng)研究中仍然缺乏一個全面的數(shù)學(xué)分析。本文一種新的數(shù)學(xué)分被開發(fā)了用于分析步進(jìn)電機(jī)的振動和不穩(wěn)定性。本文的第一部分討論了步進(jìn)電機(jī)的穩(wěn)定性分析。結(jié)果表明，中頻振蕩可定性為一種非線性系統(tǒng)的分叉現(xiàn)象（霍普夫分叉）。本文的貢獻(xiàn)之一是將中頻振蕩與霍普夫分叉聯(lián)系起來，從而霍

14、普夫理論從理論上證明了振蕩的存在性。高頻不穩(wěn)定性也被詳細(xì)討論了，并介紹了一種新型的量來評估高頻穩(wěn)定。這個量是很容易計(jì)算的，而且可以作為一種標(biāo)準(zhǔn)來預(yù)測高頻不穩(wěn)定性的發(fā)生。在一個真實(shí)電動機(jī)上的實(shí)驗(yàn)結(jié)果顯示了該分析工具的有效性。本文的第二部分通過反饋討論了步進(jìn)電機(jī)的穩(wěn)定性控制。一些設(shè)計(jì)者已表明，通過調(diào)節(jié)供應(yīng)頻率 5 ，中頻不穩(wěn)定性可以得到改善。特別是Pickup和Russell 6，7都在頻率調(diào)制的方法上提出了詳細(xì)的分析。在他們的分析中，雅可比級數(shù)用于解決常微分方程和一組數(shù)值有待解決的非線性代數(shù)方程組。此外，他們的分析負(fù)責(zé)的是雙相電動機(jī)，因此，他們的結(jié)論不能直接適用于我們需要考慮三相電動機(jī)的情況。在

15、這里，我們提供一個沒有必要處理任何復(fù)雜數(shù)學(xué)的更簡潔的穩(wěn)定步進(jìn)電機(jī)的分析。在這種分析中，使用的是d-q模型的步進(jìn)電機(jī)。由于雙相電動機(jī)和三相電動機(jī)具有相同的d-q模型，因此，這種分析對雙相電動機(jī)和三相電動機(jī)都有效。迄今為止，人們僅僅認(rèn)識到用調(diào)制方法來抑制中頻振蕩。本文結(jié)果表明，該方法不僅對改善中頻穩(wěn)定性有效，而且對改善高頻穩(wěn)定性也有效。動態(tài)模型的步進(jìn)電機(jī)本文件中所考慮的步進(jìn)電機(jī)由一個雙相或三相繞組的跳動定子和永磁轉(zhuǎn)子組成。一個極對三相電動機(jī)的簡化原理如圖1所示。步進(jìn)電機(jī)通常是由被脈沖序列控制產(chǎn)生矩形波電壓的電壓源型逆變器供給的。這種電動機(jī)用本質(zhì)上和同步電動機(jī)相同的原則進(jìn)行作業(yè)。步進(jìn)電機(jī)主要作業(yè)方式

16、之一是保持提供電壓的恒定以及脈沖頻率在非常廣泛的范圍上變化。在這樣的操作條件下，振動和不穩(wěn)定的問題通常會出現(xiàn)。圖1.三相電動機(jī)的圖解模型 用qd框架參考轉(zhuǎn)換建立了一個三相步進(jìn)電機(jī)的數(shù)學(xué)模型 。下面給出了三相繞組電壓方程va = Ria + L*dia /dt M*dib/dt M*dic/dt + dpma/dt ,vb = Rib + L*dib/dt M*dia/dt M*dic/dt + dpmb/dt ,vc = Ric + L*dic/dt M*dia/dt M*dib/dt + dpmc/dt , (1) 其中R和L分別是相繞組的電阻和感應(yīng)線圈，并且M是相繞組之間的互感線圈。pma

17、, pmb and pmc 是應(yīng)歸于永磁體 的相的磁通，且可以假定為轉(zhuǎn)子位置的正弦函數(shù)如下pma = 1 sin(N),pmb = 1 sin(N 2 /3),pmc = 1 sin(N - 2 /3), (2)其中N是轉(zhuǎn)子齒數(shù)。本文中強(qiáng)調(diào)的非線性由上述方程所代表，即磁通是轉(zhuǎn)子位置的非線性函數(shù)。使用Q ,d轉(zhuǎn)換，將參考框架由固定相軸變換成隨轉(zhuǎn)子移動的軸（參見圖2）。矩陣從a,b,c框架轉(zhuǎn)換成q,d框架變換被給出了8 (3)例如，給出了q,d參考里的電壓 (4)在a,b,c參考中，只有兩個變量是獨(dú)立的（ia + ib + ic = 0），因此，上面提到的由三個變量轉(zhuǎn)化為兩個變量是允許的。在電壓方

18、程（1）中應(yīng)用上述轉(zhuǎn)換，在q,d框架中獲得轉(zhuǎn)換后的電壓方程為vq = Riq + L1*diq/dt + NL1id + N1,vd = Rid + L1*did/dt NL1iq, (5) 圖2，a,b,c和d,q參考框架其中L1 = L + M，且是電動機(jī)的速度。有證據(jù)表明,電動機(jī)的扭矩有以下公式T = 3/2N1iq . (6)轉(zhuǎn)子電動機(jī)的方程為J*d/dt = 3/2*N1iq Bf Tl , (7) 如果Bf是粘性摩擦系數(shù)，和Tl代表負(fù)荷扭矩（在本文中假定為恒定）。為了構(gòu)成完整的電動機(jī)的狀態(tài)方程，我們需要另一種代表轉(zhuǎn)子位置的狀態(tài)變量。為此，通常使用滿足下列方程的所謂的負(fù)荷角8D/dt

19、 = 0 , (8) 其中0是電動機(jī)的穩(wěn)態(tài)轉(zhuǎn)速。方程（5），（7），和（8）構(gòu)成電動機(jī)的狀態(tài)空間模型，其輸入變量是電壓vq和vd.如前所述，步進(jìn)電機(jī)由逆變器供給，其輸出電壓不是正弦電波而是方波。然而，由于相比正弦情況下非正弦電壓不能很大程度地改變振蕩特性和不穩(wěn)定性（如將在第3部分顯示的，振蕩是由于電動機(jī)的非線性），為了本文的目的我們可以假設(shè)供給電壓是正弦波。根據(jù)這一假設(shè)，我們可以得到如下的vq和vdvq = Vmcos(N) ,vd = Vmsin(N) , (9) 其中Vm是正弦波的最大值。上述方程，我們已經(jīng)將輸入電壓由時間函數(shù)轉(zhuǎn)變?yōu)闋顟B(tài)函數(shù)，并且以這種方式我們可以用自控系統(tǒng)描繪出電動機(jī)的動

20、態(tài)，如下所示。這將有助于簡化數(shù)學(xué)分析。根據(jù)方程（5），（7），和（8），電動機(jī)的狀態(tài)空間模型可以如下寫成矩陣式 = F(X,u) = AX + Fn(X) + Bu , (10) 其中X = iq id T, u = 1 Tl T 定義為輸入，且1 = N0 是供應(yīng)頻率。輸入矩陣B被定義為矩陣A是F(.)的線性部分，如下Fn(X)代表了F(.)的線性部分，如下輸入端u獨(dú)立于時間，因此，方程（10）是獨(dú)立的。在F(X,u)中有三個參數(shù)，它們是供應(yīng)頻率1，電源電壓幅度Vm和負(fù)荷扭矩Tl。這些參數(shù)影響步進(jìn)電機(jī)的運(yùn)行情況。在實(shí)踐中，通常用這樣一種方式來驅(qū)動步進(jìn)電機(jī)，即用因指令脈沖而變化的供應(yīng)頻率1來控

21、制電動機(jī)的速度，而電源電壓保持不變。因此，我們應(yīng)研究參數(shù)1的影響。3.分叉和中頻振蕩，設(shè)=0，得出方程（10）的平衡且是它的相角， = arctan(1L1/R) . (16) 方程（12）和（13）顯示存在著多重均衡，這意味著這些平衡永遠(yuǎn)不能全局穩(wěn)定。人們可以看到，如方程（12）和（13）所示有兩組平衡。第一組由方程（12）對應(yīng)電動機(jī)的實(shí)際運(yùn)行情況來代表。第二組由方程（13）總是不穩(wěn)定且不涉及到實(shí)際運(yùn)作情況來代表。在下面，我們將集中精力在由方程（12）代表的平衡上。附件2：外文原文 The Stepper motor control circuit be based on Single ch

22、ip microcomputerThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 inst

23、ruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and

24、cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip

25、oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functi

26、oning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inpu

27、ts. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flas

28、h programming,and outputs the code bytes during programverification. External pullups are required during programverification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are p

29、ulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-di

30、rectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the

31、 internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit a

32、ddresses, Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source

33、 four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the

34、AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address duri

35、ng accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped durin

36、g each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is

37、in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VP

38、PExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal prog

39、ram executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscilla

40、tor CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should

41、 be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be

42、observed. Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain un

43、changed during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset alg

44、orithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be on

45、e that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated

46、. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memor

47、y Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a r

48、eset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.IntroductionStepper motors are electromagnetic incremental-

49、motion devices which convert digital pulse inputs to analog angle outputs. Their inherent stepping ability allows for accurate position control without feedback. That is, they can track any step position in open-loop mode, consequently no feedback is needed to implement position control. Stepper mot

50、ors deliver higher peak torque per unit weight than DC motors; in addition, they are brushless machines and therefore require less maintenance. All of these properties have made stepper motors a very attractive selection in many position and speed control systems, such as in computer hard disk drive

51、rs and printers, XY-tables, robot manipulators, etc.Although stepper motors have many salient properties, they suffer from an oscillation or unstable phenomenon. This phenomenon severely restricts their open-loop dynamic performance and applicable area where high speed operation is needed. The oscil

52、lation usually occurs at stepping rates lower than 1000 pulse/s, and has been recognized as a mid-frequency instability or local instability 1, or a dynamic instability 2. In addition, there is another kind of unstable phenomenon in stepper motors, that is, the motors usually lose synchronism at hig

53、her stepping rates, even though load torque is less than their pull-out torque. This phenomenon is identified as high-frequency instability in this paper, because it appears at much higher frequencies than the frequencies at which the mid-frequency oscillation occurs. The high-frequency instability

54、has not been recognized as widely as mid-frequency instability, and there is not yet a method to evaluate it.Mid-frequency oscillation has been recognized widely for a very long time, however, a complete understanding of it has not been well established. This can be attributed to the nonlinearity th

55、at dominates the oscillation phenomenon and is quite difficult to deal with.384 L. Cao and H. M. SchwartzMost researchers have analyzed it based on a linearized model 1. Although in many cases, this kind of treatments is valid or useful, a treatment based on nonlinear theory is needed in order to gi

56、ve a better description on this complex phenomenon. For example, based on a linearized model one can only see that the motors turn to be locally unstable at some supplyfrequencies, which does not give much insight into the observed oscillatory phenomenon. In fact, the oscillation cannot be assessed unless one uses nonlinear theory.Therefore, it is significant to use developed mathematical theory on nonlinear dynamics to handle the oscillation or instability. It is worth noting th