基于FPGA的相位差測量模塊的設(shè)計

1、基于FPGA的相位差測量模塊的設(shè)計相位差測量設(shè)計思路相位差測量設(shè)計要求 基于FPGA設(shè)計一個測量兩路同頻率信號相位差的模塊，具體要求如下： 測量信號頻率范圍： 20Hz20kHz ，精度：2度，測量波形： 方波。自行設(shè)計相位差可控雙路輸出脈沖源作為被測對象。發(fā)揮部分：（1）相位差和頻率交替顯示或同時顯示（2）提高測量精度（3）拓寬頻率范圍到20Hz200kHz（4）設(shè)計出一套相位計前置整形電路方案（采用模擬電路或者模數(shù)混合，僅設(shè)計和仿真，不制作），要求能自適應(yīng)峰峰值在0.2V至5伏的非方波輸入信號，盡量減少兩路輸入信號幅度不一致引入的誤差，帶寬不小于20Hz20kHz，輸出信號能接入本課題設(shè)計

2、的相位差測量模塊。相位差測量設(shè)計方案根據(jù)題目要求，我們組把這個模塊的設(shè)計分為四個子模塊，分別為：信號源的發(fā)生、頻率計的設(shè)計、相位差的測量和四位LED相位差顯示。信號源的發(fā)生產(chǎn)生兩路同頻、相位差可控的信號；頻率計的設(shè)計是借用信號源產(chǎn)生的信號，然后根據(jù)內(nèi)部晶振產(chǎn)生閘門寬度為1秒的閘門信號，在高電平時開始計數(shù)，記得的周期個數(shù)，即信號源產(chǎn)生信號的頻率；相位差的測量是先通過測量兩路信號的上升沿之間內(nèi)部晶振的周期數(shù)，然后由此周期數(shù)換算出相位差，再通過VHDL語言內(nèi)部函數(shù)轉(zhuǎn)換成十進制數(shù)輸出到顯示模塊。RTL圖如下：模塊程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;US

3、E IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY kzys IS PORT ( CLK : IN STD_LOGIC; KG : IN STD_LOGIC; ZS : IN NATURAL; KG_OUT: OUT STD_LOGIC );END entity kzys;ARCHITECTURE one OF kzys ISSIGNAL CNT: NATURAL;BEGIN PROCESS(KG,CLK) BEGIN IF KG=0 THEN CNT=0; KG_OUT=0; ELSIF CLKEVENT AND CLK=1 THEN IF CNTZS THEN CNT

4、=CNT+1; ELSE KG_OUTf_out1=; y_out2f_out1=; y_out2f_out1=; y_out2f_out1=6666; y_out2f_out1=6666; y_out2f_out1=6666; y_out2f_out1=499; y_out2f_out1=499; y_out2f_out1=499; y_out2f_out1=82; y_out2f_out1=82; y_out2f_out1=82; y_out2f_out1=49; y_out2f_out1=49; y_out2f_out1=49; y_out2f_out1=0; y_out2f_out1=

5、0; y_out2=0;end case;end process;end;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY plfsq IS PORT ( clk: IN STD_LOGIC; ZS: IN NATURAL; KG: IN STD_LOGIC; F_OUT : OUT STD_LOGIC );END ;ARCHITECTURE one OF plfsq ISSIGNAL FULL: STD_LOGIC ;BEGIN PROCESS(clk)VARIABLE CNT8 :

6、 NATURAL;BEGIN IF KG=0 THEN FULL 0 THEN CNT8:=CNT8-1; ELSE CNT8 :=ZS; FULL = NOT FULL; END IF; END IF; END PROCESS ;PROCESS(clk,FULL)BEGIN IF KG=1 THEN IF clk EVENT AND clk = 1 THEN IF FULL = 1 THEN F_OUT =1; ELSE F_OUT =0; END IF; END IF;END IF;END PROCESS;END one; LIBRARY IEEE;USE IEEE.STD_LOGIC_1

7、164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY plfsqy IS PORT ( clk: IN STD_LOGIC; ZS: IN NATURAL; KG: IN STD_LOGIC; F_OUTY : OUT STD_LOGIC );END ;ARCHITECTURE one OF plfsqy ISSIGNAL FULL: STD_LOGIC ;BEGIN PROCESS(clk)VARIABLE CNT8 : NATURAL;BEGIN IF KG=0 THEN FULL 0 THEN CNT8:=CNT8-1; ELSE CNT8 :=Z

8、S; FULL = NOT FULL; END IF; END IF; END PROCESS ;PROCESS(clk,FULL)BEGIN IF KG=1 THEN IF clk EVENT AND clk = 1 THEN IF FULL = 1 THEN F_OUTY =1; ELSE F_OUTY sw_1,f_out1=a,y_out2=b);u2:kzys port map(zs=b,clk=clk,kg=kg,kg_out=c);u3: plfsqy port map(clk=clk,ZS=a, KG=C,F_OUTY=F_OUTY);u4: plfsq port map(cl

9、k=clk,ZS=a,KG=KG,F_OUT=F_OUT);END ARCHITECTURE qq;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 is port(clk,en,clr:in std_logic; count10:buffer integer range 0 to );end cnt10;architecture art of cnt10 is begin process(clk,clr,en) begin if clr=1then count10=0;

10、elsif rising_edge(clk)then if(en=1)then count10=count10+1; end if; end if; end process; end art;頻率計的設(shè)計：use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity freq_measure is Port( clk0 : in std_logic; wave1 : in std_logic; q : out integer range 0 to );end freq_measure;architecture art o

11、f freq_measure iscomponent cnt10 port(clk,en,clr:in std_logic; count10:buffer integer range 0 to );end component;signal en1,clr1 : std_logic;signal date:integer range 0 to ;begin process(clk0) variable cnt:integer range 0 to 6; begin if rising_edge(clk0) then if cnt = 0 then clr1 5 then cnt := 0;q=d

12、ate; else cnt := cnt+1;clr1 = 0;en1 wave1,en=en1,clr=clr1,count10=date);end art;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity measure_n isPort(clk,clk0,clk1:in std_logic; n_out:out std_logic_vector(15 downto 0);end measure_n;architecture

13、 art of measure_n issignal count0,count01,count02,count1,count2 : std_logic_vector(15 downto 0);signal x,y,a,clk10,clk11,clk20,clk21: std_logic;beginprocess(clk,clk0,clk1,x,y,count1,count2)beginif clkevent and clk=1then case a iswhen 0=clk10=clk0;clk11=clk1; if clk10=0 and clk11=0then count10); end

14、if; if clk10=0then x=1; end if; if x=1 then if clk10=1 then if clk11=0 then y=1;end if;if y=1 then if clk11=1 then count01=count1; count1=count1;elsecount1=count1+1; end if; end if; end if;end if;if count01=0 thena=1;else a clk20=clk1; clk21=clk0; if clk20=0 and clk21=0then count20); end if; if clk2

15、0=0then x=1; end if; if x=1 then if clk20=1 then if clk21=0 then y=1; end if; if y=1 then if clk21=1 then count02=count2; count2=count2; else count2=count2+1; end if; end if; end if; end if; if count02=0 then a=0; else aa=1; end case; count0=count01 or count02;end if;n_out=count0;end process;end art

16、;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity consider1 isport ( clk :in std_logic; n1:in std_logic_vector(15 downto 0); freq:in integer range 0 to ; cout:out std_logic_vector(15 downto 0) ); end consider1; architecture arch of consider

17、1 is signal c0,c1,e,e0,d0,d1:integer range 0 to ; signal count:std_logic_vector(15 downto 0); signal m:std_logic_vector(15 downto 0); begin process(n1,clk) begin if rising_edge(clk) then m=n1; c0=conv_integer(m); d0=c0*151; d1=d0/1024; end if; end process; process(clk,freq) begin if rising_edge(clk)

18、 then c1=freq; e=c1*d1; e0=e/2048; count=conv_std_logic_vector(e0,16); end if; end process; cout=count; end arch;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity count isport( clk:in std_logic; c_in:in std_logic_vector(15 downto 0);qa1,qb1,

19、qc1,qd1:out INTEGER RANGE 0 TO 9);End count;architecture art of count isSignal a:integer range 0 to ; signal m: std_logic_vector(15 downto 0);BeginProcess(clk,c_in)variable ai,bi,ci,di:integer range 0 to 9;beginif clkevent and clk=1 then m=c_in;a=conv_integer(m);di:=(a-ai-10*bi-100*ci) /1000;ci:= (a

20、-ai-10*bi)/100;bi:= (a-ai) rem 100)/10;ai:=a rem 10;end if;qd1=di;qc1=ci;qb1=bi;qa1clkin,clk0=clk0in,clk1=clk1in,n_out=d);u2: freq_measure port map(clk0=clkin,wave1=clk0in,q=e);u3: consider1 port map(clk=clkin,n1=d,freq=8192,cout=f);u4: count port map(clk=clkin,c_in=f,qa1=qa1out,qb1=qb1out,qc1=qc1out,qd1=qd1out);end art;四位LED相位差顯示：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY BCD7 IS PORT(BCD:IN INTEGER RANGE 0 TO 9; LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END;ARCHITECTURE ART OF BCD7 IS BEGIN LED= WHEN BCD= 0 ELSE WHEN BCD= 1 ELSE WHEN BCD= 2 ELSE W