姜書艷數(shù)字邏輯設(shè)計及應(yīng)用17

1、1,Chapter 7 Sequential Logic Design Principles( 時序邏輯設(shè)計原理 ),Latches and Flip-Flops (鎖存器和觸發(fā)器 ) Clocked Synchronous State-Machine Analysis (同步時序分析) Clocked Synchronous State-Machine Design (同步時序設(shè)計),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),2,Introduction,Combinational circuit Outputs depend sole

2、ly on the present combination of the circuit inputs values,Vs. sequential circuit: Has “memory” that impacts outputs too,3,Basic Concepts (基本概念),Logic Circuits are Classified into Two Types (邏輯電路分為兩大類)： Combinational Logic Circuit （組合邏輯電路） Sequential Logic Circuit （時序邏輯電路）,Digital Logic Design and A

3、pplication (數(shù)字邏輯設(shè)計及應(yīng)用),4,Basic Concepts (基本概念),Combinational Logic Circuit （組合邏輯電路）,Outputs Depend Only on its Current Inputs. (任何時刻的輸出僅取決與當(dāng)時的輸入),Character of Circuit: No Feedback Circuit, No Memory Device (電路特點：無反饋回路、無記憶元件),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),5,Basic Concepts (基本概念),Se

4、quential Logic Circuit （時序邏輯電路）,Outputs Depend Not Only on its Current Inputs, But also on the Past Sequence of Inputs. (任一時刻的輸出不僅取決與當(dāng)時的輸入， 還取決于過去的輸入序列),Character of Circuit: Have Feedback Circuit, Have Memory Device (電路特點：有反饋回路、有記憶元件),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),6,Basic Concept

5、s (基本概念),Sequential Logic Circuit （時序邏輯電路）,Finite-State Machine: Have Finite States. (有限狀態(tài)機：有有限個狀態(tài)。）,A Clock Signal is Active High if state changes occur at the clock Rising Edge or when the clock is High, and Active Low in the complementary case. (時鐘信號高電平有效是指在時鐘信號的上升沿或時鐘的高電平期間發(fā)生變化。）,Digital Logic D

6、esign and Application (數(shù)字邏輯設(shè)計及應(yīng)用),7,Basic Concepts (基本概念),Sequential Logic Circuit （時序邏輯電路）,Clock Period: The Time between Successive transitions in the same direction. (時鐘周期：兩次連續(xù)同向轉(zhuǎn)換之間的時間。）,Clock Frequency: The Reciprocal of the Clock Period (時鐘頻率：時鐘周期的倒數(shù)。）,Digital Logic Design and Application (數(shù)字邏

7、輯設(shè)計及應(yīng)用),Figure 7-1,8,Basic Concepts (基本概念),Sequential Logic Circuit （時序邏輯電路）,Clock Tick: The First Edge of Pulse in a clock period or sometimes the period itself. (時鐘觸發(fā)沿：時鐘周期內(nèi)的第一個脈沖邊沿，或時鐘本身。）,Duty Cycle: The Percentage of time that the clock signal is at its asserted level. (占空比：時鐘信號有效時間與時鐘周期的百分比。）,

8、Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),Figure 7-1,9,思考：能否只用一片1位 全加器進行串行加法？,利用反饋和時鐘控制,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),10,需要具有記憶功能的邏輯單元，能夠暫存運算結(jié)果。,利用反饋和時鐘控制,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),11,7.1 Bistable Elements (雙穩(wěn)態(tài)元件),1,1,0,0,It has Two Stable State: Q =

9、1 ( HIGH ) and Q = 0 ( LOW ) (電路有兩種穩(wěn)定狀態(tài)：Q = 1 ( 1態(tài) ) 和 Q = 0 ( 0態(tài) ) Bistable Circuit（雙穩(wěn)電路）,0,0,1,1,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),12,7.1 Bistable Elements (雙穩(wěn)態(tài)元件),1,1,0,0,When Power is first Applied to the circuit, it Randomly Comes up in One State or the Other and Stays there Fore

10、ver. ( 只要一接電源，電路就隨機出現(xiàn)兩種狀態(tài)中的一種， 并永久地保持這一狀態(tài)。),0,0,1,1,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),13,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),14,Metastable Behavior(亞穩(wěn)態(tài)特性),Random Noise will tend to Drive a circuit that is Operating at the Metastable Point toward one of the Stable operatin

11、g point. ( 隨機噪聲會驅(qū)動工作于亞穩(wěn)態(tài)點的電路轉(zhuǎn)移到一個穩(wěn)態(tài)的工作點上去 ),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),15,所有的時序電路對亞穩(wěn)態(tài)都是敏感的,Metastable Behavior(亞穩(wěn)態(tài)特性),亞穩(wěn)態(tài),Apply a definite Pulse Width from a Stable state to the Other. (從一個“穩(wěn)態(tài)”轉(zhuǎn)換到另一個“穩(wěn)態(tài)” 需加一定寬度的脈沖（足夠的驅(qū)動）),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),16,7.2

12、Latches and Flip-Flops(鎖存器與觸發(fā)器), The Basic Building Blocks of most Sequential Circuits. (大多數(shù)時序電路的基本構(gòu)件) Latches（鎖存器） 根據(jù)輸入，直接改變其輸出（無使能端） 有使能端時，在使能信號的有效電平之內(nèi)都可根據(jù)輸入直接改變其輸出狀態(tài),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),17,7.2 Latches and Flip-Flops(鎖存器與觸發(fā)器), The Basic Building Blocks of most Sequenti

13、al Circuits. (大多數(shù)時序電路的基本構(gòu)件) Flip-Flops（ F/F,觸發(fā)器） 只在時鐘信號的有效邊沿改變其輸出狀態(tài),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),18,S-R Latch (S-R鎖存器) S-R Latch with Enable (具有使能端的S-R鎖存器) D Latch (D鎖存器) Edge-Triggered D Flip-Flops (邊沿觸發(fā)式D觸發(fā)器) Edge-Triggered D Flip-Flops with Enable (具有使能端的邊沿觸發(fā)式D觸發(fā)器),Digital Log

14、ic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),7.2 Latches and Flip-Flops(鎖存器與觸發(fā)器),19,Scan Flip-Flops (掃描觸發(fā)器) Master/Slave Flip-Flops (S-R、J-K） (主從式觸發(fā)器) Edge-Triggered J-K Flip-Flops (邊沿觸發(fā)式J-K觸發(fā)器) T Flip-Flop (T觸發(fā)器),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),7.2 Latches and Flip-Flops(鎖存器與觸發(fā)器),20,S-R L

15、atches (S-R鎖存器),（1）S = R = 0,電路維持原態(tài),工作原理：,Qn+1 = Qn QLn+1 = QLn,新 態(tài),原 態(tài),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),21,工作原理：,（2）S = 0, R = 1,a. 原態(tài)：Qn=0，QLn=1,0,1,新態(tài)：Qn+1=0，QLn+1=1,b. 原態(tài)：Qn=1，QLn=0,新態(tài)：Qn+1=0，QLn+1=1,鎖存器清0：Qn+1=0 QLn+1=1,即使S,R無效（=0） 鎖存器仍能鎖定0態(tài),Reset,1,Digital Logic Design and Appl

16、ication (數(shù)字邏輯設(shè)計及應(yīng)用),S-R Latches (S-R鎖存器),22,工作原理：,（3）S = 1, R = 0,a. 原態(tài)：Qn=1，QLn=0,1,0,新態(tài)：Qn+1=1，QLn+1=0,b. 原態(tài)：Qn=0，QLn=1,新態(tài)：Qn+1=1，QLn+1=0,鎖存器置1：Qn+1=1 QLn+1=0,即使S,R無效（=0） 鎖存器仍能鎖定1態(tài),Set,1,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),S-R Latches (S-R鎖存器),23,工作原理：,（3）S = R = 1,Qn+1 = QLn+1 = 0,當(dāng)S

17、,R無效（=0）時，,亞穩(wěn)態(tài)，對噪聲敏感 狀態(tài)不確定,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),S-R Latches (S-R鎖存器),24,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),S-R Latches (S-R鎖存器),Logic Symbol,Function Table,25,狀態(tài)圖,Qn+1 = S + RQn,SR = 0,約束條件,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),26,傳播延遲,最小脈沖寬度,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),Figure 7-8,27,S-R鎖存器的動作特點,輸入信號在全部有效電平內(nèi)，都能直接改變鎖存器的狀態(tài)（直接置位復(fù)位觸發(fā)器） 輸入端需遵守約束條件 抗干擾能力最低 當(dāng)S=R=1，然后同時取消時 S和R端輸入信號脈沖寬度過小 S和R端輸入信號同時取反,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),28,第7章作業(yè),7.4(7.2) 7.5(7.3) 7.7(7