XUPembedded_BUAA-謝凱年.doc

本文由fac5438貢獻(xiàn) pdf文檔可能在WAP端瀏覽體驗(yàn)不佳。建議您優(yōu)先選擇TXT，或下載源文件到本機(jī)查看。 贏得嵌入式教育的挑戰(zhàn) Winning the Challenge of Embedded System Education Kevin Xie XUP China Manager July, 2007 Agenda Embedded System Education Challenge Xilinx Overview Winning the Challenge -2- Embedded System is in everywhere -3- Embedded System Education Challenge MPU: 8 bit: 16 bit: 32 bit: DSP: 8051, Xilinx Picoblaze, . ARM, MIPS, PowerPC,X86, Xililinx Micoblaze . TI, ADI OS: Linux , uclilnx, Vxworks, ucOS Peripheral: ASSP, ASIC, CPLD, FPGA SOC: System On Chip ( Hardware & Software) -4- Which one should I teach? 授人以漁并且授人以魚(yú) ? Teach how to fishing and give the fish ? 課程基礎(chǔ)教育 + 技能教育 -5- Skills must have SW: GNU tool Chain ( for C code) Linux HW: 8051 ARM CPLD -6- Skills nice to have SW: Vxworks UcOS Windows CE / Windows Mobile Linux Device Driver SOC firmware HW: PowerPC MIPS DSP -7- Skills for future ? ? ? ? ? ? FPGA based DSP design ESL (Electronics System Level Design) Hardware/Software co-design High level Design language Multi-core system SOC design Reconfigurable computing -8- Source: EMF -9- Source: -10- Agenda Embedded System Education Challenge Xilinx Overview Winning the Challenge -11- XILINX Introduction Ross Freeman是Xilinx創(chuàng)始人 之一，發(fā)明了“現(xiàn)場(chǎng)可編程門(mén) 陣列”（FPGA）這種新型可編 程邏輯。 Bernie Vonderschmitt是Xilinx創(chuàng)始 人之一，提出了“無(wú)工廠”半導(dǎo)體這 一創(chuàng)新理論。 -12- What is FPGA Field Programmable Gate Array- a programmable integrated circuit. ? 可以自行設(shè)計(jì)并立即生效的集成電路 -13- -14- Xilinx Revenue Xilinx Revenue $1.73B in 2005 $1.73B in 2005 500 450 400 350 300 250 200 150 100 50 0 Q1 9 1 Q3 9 1 Q1 9 2 Q3 9 2 Record Revenue & Beyond Our Peak Xilinx $481M Xilinx $481M in Q206 in Q206 In Millions of U.S. Dollars Lattice Actel QuickLogic Q1 9 3 Q3 9 3 Q1 9 6 Q3 9 6 Q1 9 7 Q3 9 7 Q1 9 8 Q3 9 8 Q1 9 9 Q3 9 9 Q1 0 0 Q3 0 0 Q3 0 1 Q1 0 2 Q3 0 2 Q1 0 3 Q3 0 3 Q1 0 4 Q3 0 4 Q1 0 5 Q3 0 5 Q1 0 6 Q1 9 4 Q3 9 4 Q1 9 5 Q3 9 5 Q1 0 1 Q3 0 6 Revenue by calendar quarter Source: Company Reports (LSCC, ALTR, ACTL, XLNX, QUIK) -15- Triple Play: Fueling the Need for High Performance Programmable Solutions Consumer Voice Processed Wired Comms Wireless Data Automotive Digitized Video Transported AVB Aero/Defense ISM Storage & Servers Market requirements ? Flexibility to make changes, evolving standards ? Time-to-market, time-in-market ? Performance & capability ? Power, Cost, Size -16- The “NEW” FPGA Platform High Performance Processing Embedded Software Connectivity MAC (Media Access) Decision oriented tasks CORBA RTOS NBAP SCA (JTRS radios) DUC,DDC CFR,DPD RACH Searcher OFDM PHY TCC MIMO High MIPs tasks Radio PHY Supported by embedded DSP tiles, distributed memory, block memory and logic fabric DAC DAC ADC ADC EMIF SRIO Logic & IO OBSAI/CPRI SRIO AD/DA interface EMIF Serial Gigabit OBSAI/CPRI Proprietary serial backplane Inter-chip connectivity -17- Broad Range of Price/Performance 700 600 500 Mont Blanc Virtex-5 Virtex-4, 450 MHz MHz 400 300 200 100 150 MHz, 120 DMIPS Virtex-II Pro Virtex-5 Virtex-4 Mont Blanc 200 MHz, 160 DMIPS Virtex-II Pro Spartan-3 100 MHz, 92 DMIPS Spartan-3E 100 MHz, 92 DMIPS Trilogy Next Generation Spartan CoolRunner-II 2000 -18- 2002 2004 2006 2008 2010 PowerPC ? ? ? ? Hard core Open hardware license from P if migrate to ASIC Up to 4 core Up to 500MHZ Standard OS support: Vxwork, Linux, Motavisa -19- Microblaze: 32 bit soft core -20- Picoblaze ? ? ? 8 bit Microcontroller Soft core Source code available Tiny size, can fit into CPLD -21- -22- ARM Cortex What is ARM Cortex-M1? ? ? Cortex-M1 soft processor core is ARMs first processor designed specifically ? for FPGA implementation and product deployment. This is a departure from ? ARMs past policy of licensing ARM cores to FPGA users for prototyping ? only. ? ? Cortex-M1 is a 3-stage, 32-bit RISC core that supports a subset of the ? compressed 16-bit Thumb2 instruction set. It is backwards compatible with ? the popular ARM7TDMI Thumb Instruction set. -23- -24- Other soft cores ? ? ? LEON OpenRics Openfire -Microblaze .MIPS -25- Why FPGAs for High Perf. DSP? Parallelism enables very high sample rates. Conventional DSP Processor - Serial 1 GHz 256 clock cycles = 4 MSPS Note 4MSPS is a theoretical maximum Realistically it is probably 1MSPS FPGA-based DSP - Parallelism 500 MHz 1 clock cycle = 500 MSPS -26- Matlab/Simulink XILINX DSP design flow Simulation ISIM Real-Time Verification -27- Spartan-3AN, A real FPGA SOC Security solution vulnerable to cloning and overbuilding ? Worlds largest amount of user flash for embedded processing, running an OS. ? Spartan-3AN -28- Leading Edge Technology Will Continue to Fuel Xilinx Innovation 180 nm New process technology drives down cost FPGAs will be able to take advantage of new technology faster than ASICs and ASSPs 150 nm 130 nm First to 300mm Low cost 90 nm 65 nm 45 nm 32 nm First to 90nm Low cost First to triple oxide Low power 12 layer copper, 1 volt core 1.0 Volt As technology progresses down the process curve, only companies that can amortize their investment over many customers and designs will be able to afford to design their own ICs -29- Prepare for future: RAMP/BEE2 What should we do if we have 10,000 CPU in one Chip ? RAMP: A Research Accelerator for Multiple Processors 1.5W / computer, 5 cu. in. /computer, $100 / computer 1000 CPUs : 1.5 KW, ? rack, $100,000 -30- RAMP -31- -32- O The result is better than I expected. On V2P board, it works so fast that its now faster than a Gigaherz PC, quite exciting. :) Wei Sun, Technical University Eindhoven -33- 福布斯：Programmable Logic Set to Boom -34- XUP introduction ? ? ? ? XILINX University Program Start from 1985 1800 university registered Almost all key U.S. universities using XILINX technology In U.S. and European universities, FPGA = XILINX -35- Xilinx technologies in education ? ? ? ? ? ? ? ? ? ? Digital design Computer networking Digital communications Computer Architecture Control Systems Parallel processing Neural networks Evolvable systems Reconfigurable computing System on chip Error detection and correction -36- ? ? ? ? ? ? ? ? ? ? Embedded processing Real-time systems LINUX for embedded systems Cryptography Compression/decompression Industrial control Digital signal processing Video processing Genomics Hardware software co-design Robotics 3 Range of XUP boards Virtex-II Pro 399$ (China) For advanced courses : DSP, Embedded projects & research Spartan-3E 149$ For Linux/networked processor courses NEXYS 99$ BASYS 59$ For logic/processor courses For introductory logic courses -37- Stanford EE109: networked imaging -38- -39- -40- Web-case service CAE will contact customer and professor in 48 hours /support /support/clearexpress/websupport.htm -41- Joining the Xilinx University Program /univ -42- Agenda Embedded System Education Challenge Xilinx Overview Winning the Challenge -43- Skills must have SW: GNU tool Chain ( for C code) Linux HW: 8051 ARM CPLD -44- Skills nice to have SW: Vxworks UcOS Windows CE / Windows Mobile Linux Device Driver SOC firmware HW: PowerPC MIPS DSP -45- Skills for future ? ? ? ? ? ? FPGA based DSP design ESL (Electronics System Level Design) Hardware/Software co-design High level Design language Multi-core system SOC design Reconfigurable computing -46- Casestudy: ? ? ? ? ? ? ECE802-604 Embedded Systems Spring 2006 Instructor information Dr. Peixin Zhong 2211 Engineering Building Phone: (517) 432-4616 Email: Textbook ? Wolf. Computers as Components Principles of Embedded Computing System Design. ? Publisher: Morgan Kaufmann; 1st edition (October 25, 2000). ISBN: 155860541X -47- ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? This course is organized into two portions. The first provides the basic knowledge of embedded system design. It includes embedded computer architecture (ARM and SHARC are used as examples.), system organization, programming, real-time operating system (MicroC/OS-II is used as example), hardware accelerators and networks. The second half is devoted to advanced topics, including advanced embedded computer architectures using very long instruction word (VLIW), SystemC modeling, HW-SW codesign, and additional topics as time permits. You can choose either a design project or a research project. Team project is encouraged. You are also encouraged to combine the project with your own research interest. Design tools and simulation tools are used to provide the design experience. Compilers and simulators are available for multiple platforms (ARM, SHARC, MSP430, PowerPC, MicroBlaze, VLIW etc.). Mentor Graphics Seamless CVE is used for HW-SW cosimulation. ModelSim simulator enables cosimulation with SystemC, VHDL and Verilog. Complete Xilinx tool is available. Xilinx FPGA boards are available to students interested in hands on design experience. Such boards support embedded PowerPC processor cores (Xilinx Virtex Pro with embedded PPC 405) and MicroBlaze soft processor cores (Virtex Pro and Spartan 3 boards). You can implement a whole system with both software and custom hardware on one chip. You can choose either a design project or a research project. For RTOS, we will use MicroC/OS-II. It runs on Windows PC. It has also been ported to MicroBlaze and PowerPC 405. They can be implemented on the FPGA board. -48- Casestudy: Embedded System Design, A unified Hardware/Software introduction ? /sedwards/classes/2004/484 0/ XILINX XUP board -49- Wayne Wolf Embedded Computer Architectures in the MPSoC Age ? ? ? ? ? ? ? ? ? ? ? ? Wayne Wolf Dept. of Electrical Engineering Princeton University Instructors can select from among a large number of uniprocessors, but it is har