實現(xiàn)任意整數(shù)分頻電路設(shè)計

1、現(xiàn)代數(shù)字系統(tǒng)設(shè)計實現(xiàn)任意整數(shù)分頻電路設(shè)要求：占空比 50%，分頻系數(shù)可以通過撥碼開關(guān)設(shè)定。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity fenpin is port(input : in std_logic_vector(7 downto 0);led1: out std_logic_vector(6 downto 0);led2: out std_logic_vector(6 downto 0);clk_in : in s

2、td_logic; clk_out : out std_logic);end entity fenpin;architecture div of fenpin is component decoder is decoderport(bin : in std_logic_vector(3 downto 0);de : out std_logic_vector(6 downto 0); end component;signal clk_outQ : std_logic ;signal coutQ : std_logic_vector (7 downto 0); signal cout1,cout2

3、 : std_logic_vector(7 downto 0);signal clk1,clk2 : std_logic;signal a : std_logic;beginu1: decoder port map(bin=input(3)&input(2)&input(1)&input (0),de=led1);u2: decoder port map(bin=input(7)&input(6)&input(5)&input (4),de=led2);process(clk_in)beginif clk_inevent and clk_in = 1 then - 時鐘上升沿 if coutQ

4、 (conv_integer(input)-1 ) thencoutQ = coutQ + 1;- 計數(shù)else coutQ 0);- 清零end if;if coutQ (conv_integer(input)/2 then clk_outQ = 0;else clk_outQ = 1;end if;- 如果計數(shù)沒有達(dá)到 input/2,clk_outQ 為 0，達(dá)到為 1 end if;end process;process(clk_in)rising edgebeginif clk_inevent and clk_in=1 then- 輸入時鐘上升沿 if cout1 (conv_int

5、eger(input)-1) thencout1 = cout1 + 1;else cout1 0); end if;if cout1 (conv_integer(input)-1)/2 thenclk1 = 1;else clk1 = 0;end if;- 高電平跳轉(zhuǎn)到低電平，每個周期低電平時間長 end if;end process;process(clk_in)falling edgebeginif clk_inevent and clk_in=0 then- 下降沿 if cout2 (conv_integer(input)-1) thencout2 = cout2 + 1;else cout2 0); end if;if cout2 (conv_integer(input)-1)/2 thenclk2 = 1;else clk2 = 0;end if;- 高電平跳轉(zhuǎn)到低電平，低電平時間長 end if;end process;process(clk_outQ,clk1,clk2)beginif (conv_integer(input) mod 2)=0)thenclk_out = clk_outQ;-input 為偶數(shù) elseclk_out de de de