桂林電子科技大學(xué)系統(tǒng)試驗(yàn)報(bào)告

1、GUILIN UNIVERSITY OF ELECTRONIC TECHNOLOGY計(jì)算機(jī)組成系統(tǒng)實(shí)驗(yàn)課程設(shè)計(jì)報(bào)告題 目 嵌入式CISC模型計(jì)算機(jī)設(shè)計(jì)（B類）院（系）：研究生學(xué)院專 業(yè)：計(jì)算機(jī)應(yīng)用技術(shù)學(xué)生姓名：周潔學(xué) 號(hào)：102031129指導(dǎo)教師：陳智勇職 稱：副教授2011年05月22日1.1實(shí)驗(yàn)題目11.1.1實(shí)驗(yàn)的題目11.2實(shí)驗(yàn)的具體步驟11.2.1 CISC模型機(jī)數(shù)據(jù)通路框圖11.2.2操作控制器的邏借結(jié)構(gòu)框圖11.2.3機(jī)器指令格式和指令系統(tǒng)11.2.4時(shí)序產(chǎn)生器電路21.2.5微程序流程圖21.2.6操作控制器單元（即微程序控制器）31.2.7嵌入式CISC模型計(jì)算機(jī)的頂層電路

2、圖51.2.8匯編語言源程序51.2.9機(jī)器語言源程序51.2.10機(jī)器語言源程序的功能仿貞波形圖及結(jié)果分析61.2.11故障現(xiàn)象和故障分析61.2.12心得體會(huì)61.2.13軟件清單71.1實(shí)驗(yàn)題目1.1.1實(shí)驗(yàn)的題設(shè)計(jì)一臺(tái)嵌入式CISC模型計(jì)算機(jī)（采用左長CPI；周期），并運(yùn)行能完成一泄功能的機(jī)器語言程序進(jìn)行驗(yàn)證, 程序功能為：輸入包含10個(gè)整數(shù)（8位二進(jìn)制補(bǔ)碼表示）的數(shù)組M （不采用RAM）,輸出最小負(fù)數(shù)。（要求采用 P3測(cè)試）1.2實(shí)驗(yàn)的具體步驟1.2.1 CISC模型機(jī)數(shù)據(jù)通路框圖外部時(shí)鐘 復(fù)位信號(hào)說明：范例中設(shè)汁時(shí)，外部時(shí)鐘信號(hào)上邊沿有效。1.2.2操作控制器的邏輯結(jié)構(gòu)框圖指冬奇存

3、羔IR說明：在T4內(nèi)形成微指令的微地址，并訪問控制存儲(chǔ)器，在T2的上邊沿到來時(shí)，將讀出的微指令打入微 指令寄存器，即圖中的微命令寄存器和微地址寄存器。1.2.3機(jī)器指令格式和指令系統(tǒng)由此可見，本模型機(jī)中的指令系統(tǒng)中共有8條基本指令，下表列出了每條指令的格式、匯編符號(hào)和指令功 能。助記符號(hào)指令格式功能INI Rd10 0 0X XRd將數(shù)據(jù)存到Rd寄存器0UT1 Rs1111RsX X(Rs) -LEDCMP Rs, Rd10 10RsRd(Rs)-(Rd),鎖存 CY 和 ZI,SFINC Rd110 1X XRd(Rd)+1-RdMOV Rd, data10 0 1X XRddata-*Rd

4、dataJMP addr1110XXXXaddr-*PCaddrJB addr10 11XXXX若小于，則addr-*PCaddrMovl Rs, Rd110 0RsRd(Rs) -Rd說明:對(duì)Rs和Rd的規(guī)定:Rs 或 Rd選立的寄存器00RO01R110R211R3模型機(jī)規(guī)泄數(shù)據(jù)的表示采用左點(diǎn)整數(shù)補(bǔ)碼表示，單字長為8位.其格式如下:76543210符號(hào)位尾數(shù)1.2.4時(shí)序產(chǎn)生器電路TK T2、T3、T4與CLR、Q之間的關(guān)系圖如下圖所示:CLRQrLTLTLmrLTLT111T2T3T4個(gè)CPU周期x圖一1.2.5微程序流程圖微程序控制器的設(shè)汁過程為:（1）根據(jù)指令格式和指令系統(tǒng)設(shè)計(jì)所有機(jī)

5、器指令的微程序流程圖，并確左每條微指令的微地址和后繼微地 址：（2）設(shè)計(jì)微指令格式和微指令代碼表：（3）設(shè)計(jì)地址轉(zhuǎn)移邏輯電路：（4）設(shè)汁微程序控制器中的其它邏輯單元電路，包括微地址寄存器、微命令寄存器和控制存儲(chǔ)器；（5）設(shè)汁微程序控制器的頂層電路（由多個(gè)模塊組成）。圖二CISC模型機(jī)中所有機(jī)器抬令的微程序流程圖126操作控制器單元（即微程序控制器）（1）設(shè)計(jì)微指令格式和微指令代碼表CISC模型機(jī)系統(tǒng)使用的微指令采用全水平型微指令，字長為25位，其中微命令字段為17位，P字段為2 位，后繼微地址為6位，其格式如下：242322212019 1S 17 1615141312 11109 S 7 6

6、5 4 3 2 1 0LOAD LDPC LDAR LDIR LDR1RS B SI SO ALU.B LDAC LDDR WR CS SW B LED B LDFR Pl P2 )亍繼微地址由微指令格式和微程序流程圖編寫的微指令代碼表如下所示，在微指令的代碼表中微命令字段從左邊到右 代表的微命令信號(hào)依次為：LOAD、LDPC、LDAR、LDIR、LDRi、RD_B、RS_B、SI. SO、ALU_B、LDAC、LDDR、WR> CS、 SW B. LED B、 LDFR。微地址微命令字段PlP2P3后繼微地址000000111001100100111100000000100000101

7、001011001001011010000100000001110001110010010110000000000000100100000100101111100000001010001011000011011001111100000000000100010001110010011010000000000001001111001100100111100000000110010101000010001101111000000010000101111100110010011110001001111001100100011000100111100000000000011011000001001101

8、1110000010010001110111001100100111100000100110011111000010001000110000000000001001010001111000011110000000000010011010001100100101100000000000011110100011001001011000000000010001110000110010011110000000000(2)設(shè)計(jì)地址轉(zhuǎn)移邏輯電路地址轉(zhuǎn)移邏輯電路是根據(jù)微程序流程圖3-2中的棱形框部分及多個(gè)分支微地址，利用微地址寄存器的異步 置“1”端，實(shí)現(xiàn)微地址的多路轉(zhuǎn)移。由于微地址寄存器中的觸發(fā)器異步置“

9、1”端低電平有效，與臥4AAO對(duì)應(yīng)的異步置“1”控制信號(hào)SE5 SE1的邏彎達(dá)式為：(PA5的異步置“1”端SE6實(shí)際未使用)SE6二冠 P(3) T4 SE5=(FC+FZ) P(2) T4SE4=I7>P(1) -T4SE3二I6PT4SE2二I5PT41.2.7嵌入式CISC模型計(jì)算機(jī)的頂層電路1.2.8匯編語言源程序由給岀的題目和設(shè)計(jì)的指令系統(tǒng)編寫相應(yīng)的匯編語言源程序。算法思想為：采用R1寄存器存放從開關(guān)輸入的任 意一個(gè)整數(shù)，R3存放輸入的最小負(fù)數(shù)，R0和R2用于控制循環(huán)，用一個(gè)循環(huán)程序?qū)崿F(xiàn)如下:M0V1 RO,00HM0V1 R1,OAHM0V1 R2,FFHL1:INI R3

10、INC RORO中的數(shù)自加1CMP RO, R1JB L2OUT R2L2: CMP R2,R3JB L3JMP LIMOV2 R3, R2JMP LI將0存入寄存器RO將10存入寄存器RO 將-1存入寄存器R0將輸入的數(shù)存入R3比較R0和R1的大小若R0小于R1,跳轉(zhuǎn)到L2輸岀R2比較R2和R3的大小若R2小于R3,跳轉(zhuǎn)到L3 無條件跳轉(zhuǎn)到L1將R3中的內(nèi)容移到R2無條件跳轉(zhuǎn)到L11.2.9機(jī)器語言源程序根據(jù)設(shè)訃的指令格式，將匯編語言源程序手工轉(zhuǎn)換成機(jī)器語言源程序，并將其設(shè)訃到模型機(jī)中的ROM中去。 與1.2.8中匯編語言源程序?qū)?yīng)的機(jī)器語言源程序如下：助記符 地址（十六進(jìn)制）機(jī)器代碼功能M

11、0V1 RO, 00H0010010000OOH fR00100000000M0V1 R1,OAH0210010001OAH 一R10300001010M0V1 R2,FFH0410010010FFH - R20511111111L1:INI R30610000011(SW) -R3INC RO0711010000(RO)+1_ROCMP RO, R10810100001(R0)-(Rl)JB L20910110000若小于，L2 一PCOA00001100OUT R20B11111000(R2) -LEDL2: CMP R2, R3OC10101011(R2)-(R3)JB L30D1011

12、0000L3-PC0E00010001JMP LI0F1U00000LI-PC1000000110L3: M0V2 R3,R21111001110(R3) - (R3)JMP LI1211100000Ll-P2.10機(jī)器語言源程序的功能仿真波形圖及結(jié)果分析圖四結(jié)果分析：輸入的整數(shù)依次為 81H, 80H, 34H, 88H, 99H, 23H, 12H, 37H, 65H, 86H。 結(jié)果輸出：80H。il算結(jié)果與事實(shí)相符，程序正確執(zhí)行。1.2.11故障現(xiàn)象和故障分析1. 在編譯仿真過程中，發(fā)現(xiàn)指令寄存器IR中的匯編指令執(zhí)行步驟發(fā)生錯(cuò)誤。由于頂層電路的設(shè)訃并沒有 錯(cuò)誤

13、，所以分析應(yīng)該是R0H里的指令跳轉(zhuǎn)發(fā)生錯(cuò)気 后來發(fā)現(xiàn)：在ROM器件的VHDL編程發(fā)生錯(cuò)誤，跳轉(zhuǎn)指令JMP 的跳轉(zhuǎn)地址錯(cuò)誤，導(dǎo)致了程序執(zhí)行步驟的錯(cuò)誤。2. 仿真時(shí)，輸入幾個(gè)十六進(jìn)制整數(shù)補(bǔ)碼，發(fā)現(xiàn)輸出的執(zhí)行結(jié)果并不是最小負(fù)數(shù)。后來根據(jù)觀察仿真波形圖 中寄存器R3中存放的負(fù)數(shù)，可能是因?yàn)檩斎氲恼麛?shù)時(shí)，并未經(jīng)過數(shù)據(jù)總線傳送并存放于寄存器R3中。最后分 析得岀故障原因是：每次輸入的整數(shù)，需要對(duì)應(yīng)IR中的輸入指令81H,這樣才能夠成功輸入整數(shù)，從而進(jìn)行整 數(shù)之間的比較大小。1.2.12心得體會(huì)通過這次實(shí)驗(yàn)，我基本上了解了 CISC模型機(jī)各個(gè)部件的具體工作原理，也對(duì)汁算機(jī)組成原理有了進(jìn)一步的 理解掌握。在實(shí)

14、驗(yàn)過程中，遇到了一些故障，主要還是對(duì)理論的認(rèn)識(shí)不太深刻。在不斷的發(fā)現(xiàn)問題和解決問題 的過程中，我感覺這次實(shí)驗(yàn)不僅讓我學(xué)到了許多理論知識(shí)，同時(shí)也讓我明白了：不論做什么事，都要認(rèn)認(rèn)貞真、 踏踏實(shí)實(shí)的去做，終究會(huì)取得成功。1.2.13軟件清單1ALU單元 flit 7 0 BCDOUTC 7 0：>B： 7.OCTr-：SJLZ I 5- S-OSF"1ALU單元LIBRARY IEEE;USE IEEE. STD_L0GIC_1164. ALL;USE IEEE. STD_LOGIC_ARITH ALL;USE IEEE. STD.LOGIC.UNSIGNED ALL;ENTITY

15、 ALU ISPORKA:IN STD_LOGIC_VECTOR(7 DOWNTO 0);B:IN STD_L0GIC_VECT0R(7 DOWNTO 0);SI, SO:IN STD_LOGIC;BCDOUT:OUT STD_L0GIC_VECT0R(7 DOWNTO 0);CY, ZI,SF:OUT STD.LOGIC);END ALU;ARCHITECTURE A OF ALU ISSIGNAL AA,BB,TEMP:STD_L0GIC_VECT0R(8 DOWNTO 0);BEGINPROCESS (SI, SO)BEGINIF(S1= 01 AND SO二'O')TH

16、EYAA二'O'&A;BBU' O' &B;TEMP<=AA-BB;BCDOUT<=TEMP(7 DOWNTO 0);CY<=TEMP(8);IF(TEMP="100000000" OR TEMP二"000000000”)THEN ZI<= r ;ELSEZI<= 0 ；END IF;ELSIF(S1 二'O' AND SO= DTHENBCDOUT<=A-B;IF(A(7)=0，AND B(7)=0，) OR (A(7)= T AND B(7) = 13)THEN

17、IF(A<B)THENCYUi ;ZI<= o'SFUi ;ELSIF (A=B)THENCY<=' O'zi<= r ；SF<=，0* ;ELSECYU' O'ZI<= o'SF<= O'END IF;ELSIF(A(7)= O1) AND (B(7)= D)THENCY<= r ;ZI<= O'SF<=J O'ELSIF(A(7)= T) AND (B(7)= 0>)THENCY<=J O'ZI<= 0,;SF<= r ;END

18、 IF;ELSIF(S1= r AND SOOTHENAAU' O'&A;TEMP<=AA+1；BCDOUT<=TEMP(7 DOWNTO 0);CY<=TEMP(8);IF(TEMP二100000000")THENZI<= r ;ELSEZI<= O'END IF;ELSEBCDOUT<=zOOOOOOOO"CYU' O'ZI<= o'END IF;END PROCESS:END A;2狀態(tài)條件寄存器單元LDFR FSSFC YFCFZX.A狀態(tài)條件寄存器單元LIBRARY

19、IEEE;USE IEEE. STD_L0GIC_1164ALL;USE IEEE. STD_LOGIC_ARITH. ALL;USE IEEE. STD_LOGIC_UNSIGNED. ALL;ENTITY LS74 ISPORKLDFR:IN STD.LOGIC; CY,ZI:IN STD.LOGIC;FS,FC,FZ:OUT STD_LOGIC);END LS74;ARCHITECTURE A OF LS74 ISBEGINPROCESS(LDFR)BEGINIF(LDFR，EVENT AND LDFR二'1'THEYFC二CY;FZ<=ZI;FSUSF;END I

20、F;END PROCESS;END A;3暫存寄存器單元LS27329暫存寄存器單元LIBRARY IEEE;USE IEEE. STD_LOGIC_1164ALL;ENTITY LS273 ISPORKD:IN STD_LOGIC_VECTOR(7 DOWNTO 0);CLK:IN STD.LOGIC;O:OUT STD_L0GIC_VECT0R(7 DOWNTO 0);END LS273;ARCHITECTURE A OF LS273 ISBEGINPROCESS(CLK)BEGINIF(CLK EVENT AND CLK二'1)THEN0<=D;END IF;END PRO

21、CESS;END A;43選1數(shù)據(jù)選擇器 MUX31 D 70J:SW.BC5EW匚701NJL E 7 1HE 7en3選1數(shù)據(jù)選擇器MUX3LIBRARY IEEE;USE IEEE. STD_LOGIC_1164. ALL;USE IEEE. STD_LOGIC_ARITH. ALL;USE IEEE. STD.LOGIC.UNSIGNED ALL;ENTITY MUX3 ISPORKID:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SW_B, CS:IN STD.LOGIC;N1,N2:IN STD_L0GIC_VECT0R(7 DOWNTO 0);EW:OUT S

22、TD_L0GIC_VECT0R(7 DOWNTO 0);END MUX3;ARCHITECTURE A OF MUX3 ISBEGINPROCESS(SW_B, CS)BEGINIF(SW_B 二'O') THEN EW<=ID;ELSIF(CS 二'O')THEEW<=N2;ELSEEW<=N1；END IF;END PROCESS;END A;5 5選1數(shù)據(jù)選擇器5選1數(shù)據(jù)選擇器MUX5LIBRARY IEEE;USE IEEE. STD_L0GIC_1164. ALL;ENTITY MUX5 ISPORKC, D, E, F,G:IN S

23、TD.LOGIC;Xl,X2,X3t X4,X5:IN STD_LOGIC_VECTOR(7 DOWNTO 0);W:OUT STD_L0GIC_VECT0R(7 DOWNTO 0);END MUX5;ARCHITECTURE A OF MUX5 ISSIGNAL SEL:STD_L0GIC_VECT0R(3 DOWNTO 0);BEGINSEL二F&E&D&C;PROCESS(SEL)BEGINIF(SEL二"1110") THENW<=X1;ELSIF(SEL=z110D THENW<=X2;ELSIF(SEL="101D

24、THENW<=X3;ELSIF(SELLOUT) THENW<=X4;ELSIF(SEL=z0111D THENW<=X5;ELSENULL;END IF;END PROCESS;END A;6程序計(jì)數(shù)器單元程序計(jì)數(shù)器單元PCLIBRARY IEEE;USE IEEE. STD_L0GIC_1164. ALL;USE IEEE. STD_LOGIC_ARITH. ALL;USE IEEE. STD_LOGIC_UNSIGNED. ALL;ENTITY PC ISPORKLOAD, LDPC, CLR:IN STD.LOGIC;D:IN STD_LOGIC_VECTOR(7 D

25、OWNTO 0);O:OUT STD_L0GIC_VECT0R(7 DOWNTO 0);END PC;ARCHITECTURE A OF PC ISSIGNAL QOUT:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS(LDPC,CLR, LOAD)BEGINIF(CLR= Of)THENQOUTUOOOOOOOO"ELSIF(LDPC，EVENT AND LDPC= T) THEN IF (LOAD 二'O') THENQOUT二D; BUS->PCELSEQOUT二QOUT+l; PC+1END IF;END IF;END

26、 PROCESS;OUQOUT;END A;7地址寄存器單元LS2V3nr?U -JL K.地址寄存器單元8主存儲(chǔ)器單元ROM16>AK>DR C 了 -D O UT C *7.os-主存儲(chǔ)器單元LIBRARY IEEE;2USE IEEE. STD_L0GIC_1164. ALL;USE IEEE. STD_LOGIC_ARITH. ALL;USE IEEE. STD_LOGIC_UNSIGNED. ALL;ENTITY R0M16 ISPORKADDR:IN STD_L0GIC_VECT0R(7 DOWNTO 0); CS:IN STD.LOGIC;DOUT:OUT STD.L

27、OGIC.VECTOR(7 DOWNTO 0) );END ROM16;ARCHITECTURE A OF R0M16 ISBEGIND0UT<=z10010000WN/ZOOOOOOOO/ZWHEN/z1001000rzWHEN /ZOOOO1O1OZ，WHEX /Z1OO1OO1OZ，WHEX "llllllU'WHEN "lOOOOOll'WHEN /z 11010000" WHEN "lOlOOOOlWN /Z1O11OOOOZ，WHEN "00001lOO'WHEX /Z11111OOOZ，WHEN /Z

28、1O1O111OZ，WHEN "lOUOOOO'WHEN "OOOIOOOI'WHEN "lllOOOOO'WHEN "00000110'WHENADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR"llOOlllO'WHEN ADDR "lllOOOOO'WHEN ADDR "OOOOOllO'WHEN ADDR"00000000"&

29、quot;00000001""00000010""00000011""00000100""oooooior"00000110""00000111""00001000""ooooioor"00001010"少00001011""00001100""00001101""00001110""00001111""00010000&quo

30、t;"00010001""00010010""00010011"ANDANDANDANDANDANDANDANDANDANDANDANDANDANDANDANDANDANDANDANDCSCSCSCSCSCSCSCSCSCSCSCSCSCSCSCSCSCSCSCS'o''o''O''o''o''o''o''o''o''o''o''o''o

31、''o''o''O''O''o''o'9ELSE-M0V1RO,OOHELSEELSEM0V1Rl,OAHELSEELSE-M0V1R2,FFHELSEELSE-IN1R3ELSEINCROELSECMPRO,R1ELSEJB L2ELSEELSEOUT R3ELSECMP R3, R2ELSEJB L3ELSEELSEJB LIELSEELSE-M0V2 R3, R2ELSE-JMP LIELSE"00000000"END A;9指令寄存器單元LS£73指令寄

32、存器單元10時(shí)序產(chǎn)生器單元T2:QC L R 3T4MCOUNTER時(shí)序產(chǎn)生器單元LIBRARY IEEE;USE IEEE. STD_L0GIC_1164. ALL;USE IEEE. STD_LOGIC_ARITH. ALL;USE IEEE. STD.LOGIC.UNSIGNED ALL;ENTITY COUNTER ISPORKQ, CLR:IN STD.LOGIC;T2,T3,T4:OUT STD_LOGIC);END COUNTER;ARCHITECTURE A OF COUNTER ISSIGNAL X:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINPRO

33、CESS(Q, CLR)BEGINIF (CLR 二'O') THENT2<= O'T3<= O'T4<= O' x<oo"；ELSIF© EVENT AND Q二'1' )THENX<=X+1;T2<=(N0T X(l) AND X(0);T3<=XAND (NOT X(0);T4<=X(1)AND X(0);END IF;END PROCESS;END A;11微程序控制器單元微程序控制器單元微程序控制器的內(nèi)部結(jié)構(gòu)11.1地址轉(zhuǎn)移邏輯電路ADDR1 71 &|

34、 pQ L 上1 5S E &1 <S- E. 5r Zr SSEN1 4S- E_ XRXPNP3地址轉(zhuǎn)移邏輯電路LIBRARY IEEE;USE IEEE. STD_L0GIC_1164ALL;ENTITY ADDR ISPORK17,16,15,14:IN STD.LOGIC;FZ, FC, FS, T4, Pl, P2, P3:IN STD.LOGIC;SE6, SE5,SE4, SE3,SE2, SEI:OUT STD.LOGIC );END ADDR;ARCHITECTURE A OF ADDR ISBEGINSE6<=N0T (NOT FS AND P3 AN

35、D T4)Fs二0,跳轉(zhuǎn)SE5<=N0T (NOT FC AND FZ )AND P2 AND T4)FZ二0,跳轉(zhuǎn)SE4<=N0T(I7SE3<=N0T(I6SE2<=N0T(I5SE1<=NOT(I4ANDANDANDANDPlPlPlPlANDANDANDANDT4);T4);T4);T4);END A;11.2微地址寄存器SE5 SE-qSE3SEESEJL"aUA3UAJLUACSEOTZDSD40302DX DOCLK微地址寄存器r-iMMsesI> UAS心.SE3TOT.linn:yci_nntiii廣“9 .丫ei RI1MI14

36、、UA2ririCtrn-T=> UA1-ir-inSEO -匚蘭一曲匚蘭亠Ti> UAOCLK.匚二匕吞艾 1.匚二LpSE2I 、VGC - -<微地址寄存器內(nèi)部結(jié)構(gòu)J".T2DS (D3 C-vcv-»！D2 C=>vcc7DI C=cc;.DOLIBRARY IEEE;USE IEEE. STD_LOGIC_1164ALL;ENTITY MMM ISPORKSE:IN STD.LOGIC;T2:IN STD.LOGIC;D:IN STD.LOGIC;CLR:IN STD.LOGIC;UA:OUT STD.LOGIC);END MMM;ARCH

37、ITECTURE A OF MMM ISBEGINPROCESS (CLR, SE, T2)BEGINIF(CLR= OTHEN UA<=' O'ELS IF (SE 二'O') THEN UA<= r ;ELSIF(T2' EVENT AND T2= r)THENUA<=D;END 比END PROCESS;END A;11.3微地址轉(zhuǎn)換器微地址轉(zhuǎn)換器LIBRARY IEEE;USE IEEE. STD_LOGIC_1164. ALL;ENTITY Fl ISPORKUA5, UA4, UA3, UA2, UA1, UAO: IN S

38、TD_LOGIC;D:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);END Fl;ARCHITECTURE A OF Fl ISBEGIND(5X=UA5;D(4X=UA4;D(3)<=UA3;D(2X=UA2;D(1X=UA1;D(0) <=UA0;END A;11.4控制存儲(chǔ)器CONTROMADDR 5：.0：1 U A 5：.D C JL9. e JOj8控制存儲(chǔ)器LIBRARY IEEE;USE IEEE. STD_L0GIC_1164. ALL;USE IEEE. STD_LOGIC_ARITHALL;USE IEEE. STD_LOGIC_UNSIG

39、NED. ALL;ENTITY CONTROM ISPORKADDR:IN STD丄0GIC_VECT0R(5 DOWNTO 0);UA:OUT STD_L0GIC_VECT0R(5 DOWNTO 0);D:OUT STD_L0GIC_VECT0R(19 DOWNTO 0);END CONTROM;ARCHITECTURE A OF CONTROM ISSIGNAL DATAOUT:STD.LOGIC.VECTOR(25 DOWNTO 0);BEGINPROCESS(ADDR)BEGINCASE ADDR ISWHEr000000"=>DATAOUT<=/z1110011

40、0010011110000000010"WHEr000010"=>DATAOUT<=/z10010110010010110100001000"WHEN，/0000ir=>DATAOUT<=z10001110010010110000000000zz;WHEN，/000100'=>DATAOUT<=z1000001001011111000000010r；WHEN，/00010r=>DATA0UT<=/z10000110110011111000000000"00 (02)02 (08)03 (00)04

41、(05)05 (00)-WEN'OOOllODATAOUKlOOOOOlOOlOlllllOOOOOOOlll" WEr0001U"=>DATAOUT<=/z10001110000011110000000000"WHEN，/001000"=>DATAOUT<=/，10001110010011010000000000"WHEN，/00100r=>DATAOUT<=/，U1001100100111100000000ir；WHEN，/001010"=>DATAOUT<="10

42、000100011011110000000100，/;WHEN，/0010ir=>DATAOUT<="1110011001001111000101010r；WHEN，/001100"=>DATAOUT<=/，10001100010011110000000000ZZ;wHErooiior=>DATAouT<=/ioooooioouoiiiioooooiooiozz；WHEN'OOlllODATAOUKlllOOllOOlOOllllOOOOOlOOir；WHEN'OO1111"=>DATAOUT<=Z1

43、0000100010001100000000000"WHEr010010"=>DATAOUT<=/z10001111000011110000000000"WHEN，/0100ir=>DATAOUT<=z01000110010010110000000000zz;WHEN，/01010r=>DATA0UT<=/，01000110010010110000000000"WHEN" 11010r=>DATA0UT<=z 10000110010011110000000000"WHEN OTHERS

44、二DATAOUTU" 10000110010011110000000000；08 (00)09 (03) 0A(04) OB (15)OC (00)0D(12)0E(13) OF (00) 12(00) 13(00) 15(00) 35 (00)CHANGEEND CASE;VA(5 DOWNTO 0)<=DATA0UT(5 DOWNTO 0);D(19 DOWNTO 0)<=DATAOUT(25 DOWNTO 6);END PROCESS;END A;11.5微指令寄存器T2T3TaMCOMMANDP3PlP2LOADUDPCLDARLD I RUDR1LDR2LDR3

45、RO_BRi_BJR2-BR3-BOCXS. OSJLALU_BLDACLDDRWRCS"_BUED_BLDFR微指令寄存器LIBRARY IEEE;USE IEEE. STD_LOGIC_1164ALL;USE IEEE. STD_LOGIC_ARITHALL;USE IEEE. STD_LOGIC_UNSIGNED. ALL;ENTITY MCOMMAND ISPORKT2, T3, T4,13,12, II, 10: IN STD.LOGIC; 0:IN STD_L0GIC_VECT0R(19 DOWNTO 0);P3, Pl, P2,LOAD,LDPC, LDAR, LDIR, LDRO, LDR1,LDR2, LDR3, R0_B, R1_B, R2_B, R3_B, SI, SO, ALU_B, LDAC, LDDR, WR,CS,SW_B,LED_B, LDFR: OUT STD_LOGIC );END MCOMMAND;ARCHITECTURE A OF '(COMMAND ISSIGNAL DATAOUT:STD_LOGIC_VECTOR (19 DOWNTO 0);BEGIN PROCESS(T2)BEGINIF (12? EVENT AND T2= DTHENDATAOUT(19 DOWNT