案例教案測(cè)試課1

1、IC Testing Practice 郭箏郭箏 潘文捷潘文捷 莫亭亭莫亭亭 OverviewProject Practice：48 class3 creditsPrerequisites: Knowledge of VLSI design 、Microelectronics fundamentalsGrading10% class40% practice50% final paperTextbookTextbook:No required textbookSlides available at class web page： weidianziReference Books:1、Michae

2、l L. Bushnell等著，蔣安平等譯，超大規(guī)模集成電路測(cè)試-數(shù)字、存儲(chǔ)器和混合信號(hào)系統(tǒng)，電子工業(yè)出版社，2005.08。2、雷紹充 邵志標(biāo) 梁峰等著，超大規(guī)模集成電路測(cè)試，電子工業(yè)出版社，2008。3、The Fundamentals of Digital Semiconductor Testing, Soft Test Inc., 1995。Why Test So Important?Ensures quality product Revenue stream & quality reputation is passing through the testerInsures t

3、he product meets its published specificationsCharacterize to determine device performance and providefeedback to the design team（for Design)Failure analysis provides feedback to the manufacturing team for better process control (for Manufacture not by ATE)Defects uncaught cost 10 x more to find at t

4、he next stage10c at wafer, $1 at package, $10 at PCB, $100 at systemExample Intel Pentium CPU floating dividing bugLogic error not caught until 1M units shippedRecall cost $450MObject of this CourseThis course will helps you to create your values.You will have the basic understanding of IC testYou w

5、ill have the entry level knowledge & skills to work for IC testing.You will know the right direction ,if you want to get further study & research.Course contentDUTResponse ComparatorStimulus Signal GeneratorATETest Response RTest Patterns TReference (expected) Response RPass: R=RFail: RRTest

6、 GenerationFault ModelingDesign for TestabilityTest ApplicationFaultNew ChallengesCompany：Teradyne & TI About TeradyneTI聯(lián)合測(cè)試實(shí)驗(yàn)室概況聯(lián)合測(cè)試實(shí)驗(yàn)室概況 ETS88 PEony-12測(cè)試機(jī)臺(tái)測(cè)試機(jī)臺(tái)IC industryMost growth is in Consumer applicationsWhy do people need more than one phone? Total ATE Market ShareTest Engineering is a d

7、ifficult profession!MaximizeYieldHitQualityTargetMinimizeCost of TestMinimizeTime to MarketGreat Engineers in 21st CenturyA great engineer should have a broad spectrum as well as a huge dynamic range of knowledge & skills.Lecture 1 Basic concepts and definitions IC historyVLSI realization proces

8、sVerification and testIdeal and real testsCosts of testingRoles of testingA modern VLSI device - system-on-a-chipCourse outlinePart I: Introduction to testingPart II: Test methodsPart III: Design for testabilityA Brief HistoryVacuum tubes ruled the 1st half of the 20th centuryLarge, expensive, power

9、 hungry, unreliable1947: Birth of modern electronicsAT&T Bell lab Invented point contact transistorWilliam Shockley, Walter Brittain, & John Bardeen won Nobel prize in physics in 19561958: First integrated circuitFlip-flop using two transistorsBuilt by Jack Kilby at Texas Instruments2003Inte

10、l Pentium 4 processor (55 million transistors)512 Mbit DRAM ( 0.5 billion transistors)Driven by miniaturization of transistorsSmaller is cheaper, faster, lower in power!Revolutionary effects on societyMicroelectronic RevolutionIn 1958,The First Integrated Circuit Jack Kilby, Texas Instruments1 Trans

11、istor and 4 Other Devices on 1 ChipWinner of the 2000 Nobel PrizePentium 4 mProcessor - 200355 million transistorsVLSI Realization ProcessDetermine requirementsWrite specificationsDesign synthesis and VerificationFabricationManufacturing testChips to customerCustomers needTest developmentDefinitions

12、Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes.Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.Test: A manufacturing step that ensures that the ph

13、ysical device, manufactured from the synthesized design, has no manufacturing defect.Verification vs. Test Verifies correctness of design.Performed by simulation, hardware emulation, or formal methods.Performed once prior to manufacturing.Responsible for quality of design.Verifies correctness of man

14、ufactured hardware.Two-part process:1. Test generation: software process executed once during design2. Test application: electrical tests applied to hardwareTest application performed on every manufactured device.Responsible for quality of devices. Problems of Ideal TestsIdeal tests detect all defec

15、ts produced in the manufacturing process.Ideal tests pass all functionally good devices.Very large numbers and varieties of possible defects need to be tested.Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.Real TestsBased on analyzable fault models, whi

16、ch may not map on real defects. plete coverage of modeled faults due to high complexity.Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss.Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect

17、level.Testing as Filter ProcessFabricatedchipsGood chipsDefective chipsProb(good) = yProb(bad) = 1- yProb(pass test) = highProb(fail test) = highProb(fail test) = lowProb(pass test) = lowMostlygoodchipsMostlybadchipsCosts of TestingDesign for testability (DFT)Chip area overhead and yield reductionPe

18、rformance overheadSoftware processes of testTest generation and fault simulationTest programming and debuggingManufacturing testAutomatic test equipment (ATE) capital costTest center operational cost Design for Testability (DFT)DFT refers to hardware design styles or added hardware that reduces test

19、 generation complexity.Motivation: Test generation complexity increases exponentially with the size of the circuit.Logicblock ALogicblock BPIPOTestinputTestoutputInt.busExample: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks.Pres

20、ent and Future* Transistors/sq. cm 4 - 10M 18 - 390M Pin count 100 - 900 160 - 1475Clock rate (MHz) 200 - 730 530 10kPower (Watts) 1.2 - 61 2 - 96 Feature size (micron) 0.25 - 0.15 0.13 - 0.011997 -20012003 - 2014* SIA Roadmap, IEEE Spectrum, July 1999Cost of Manufacturing Testing after 2000AD0.5-1.

21、0GHz, analog instruments,1,024 digital pins: ATE purchase price= $1.2M + 1,024 x $3,000 = $4.272MRunning cost (five-year linear depreciation)= Depreciation + Maintenance + Operation= $0.854M + $0.085M + $0.5M= $1.439M/yearTest cost (24 hour ATE operation)= $1.439M/(365 x 24 x 3,600)= 4.5 cents/secondRoles of TestingDetection: Determination whether or not the device under test (DUT) has some fault.Diagnosis: Identification of a specific fault that is present on DUT.Device characterization: Determination and correct