液晶顯示驅(qū)動(dòng)電路的設(shè)計(jì)與實(shí)現(xiàn)(4課時(shí))

1、實(shí)驗(yàn)六 液晶顯示驅(qū)動(dòng)電路的設(shè)計(jì)與實(shí)現(xiàn)（4課時(shí)）實(shí)驗(yàn)?zāi)康?.熟練掌握設(shè)計(jì)電路下載到芯片的關(guān)鍵設(shè)置與基本步驟和利用實(shí)驗(yàn)箱上的輸入信號(hào)和輸出顯示器件在線測(cè)試設(shè)計(jì)電路的方法。2.熟悉液晶顯示的原理，了解液晶顯示器件的性能特點(diǎn)、分類參數(shù)。掌握液晶顯示器件的接口時(shí)序與通訊格式。3.掌握利用VHDL語(yǔ)言設(shè)計(jì)液晶顯示器件驅(qū)動(dòng)電路的方法。實(shí)驗(yàn)原理1.中文液晶顯示模塊（OCMJ128X32）的引腳說(shuō)明引腳名稱方向說(shuō)明其它1VLED+I背光電源正極(LED+5v)2VLED-I背光電源負(fù)極(LED-5v)3VSSI地4VDDI（+5v）5REQI請(qǐng)求信號(hào)，高電平有效。6BUSYO應(yīng)答信號(hào)=1：已經(jīng)收到數(shù)據(jù)并正在處理

2、中 =0：模塊空閑，可以接受數(shù)據(jù)7-14DB0DB7I數(shù)據(jù)0數(shù)據(jù)72.接口時(shí)序說(shuō)明編號(hào)名稱單位最小值最大值說(shuō)明1TruS0.4-數(shù)據(jù)線上數(shù)據(jù)穩(wěn)定時(shí)間2TbuS220最大模塊響應(yīng)時(shí)間3TrtuS11-最小REQ保持時(shí)間4Ts1uS2045最大數(shù)據(jù)接收時(shí)間5Ts2uS-0.1-30最大命令指令處理時(shí)間3.用戶命令格式（1）實(shí)驗(yàn)用液晶顯示器模塊（OCMJ）命令幀分為操作碼及操作數(shù)兩部分。（2）字符命令：1、顯示國(guó)標(biāo)漢字，2、顯示8X8ASCII字符，3、顯示8X16ASCII字符 圖形顯示命令：4、顯示位點(diǎn)陣，5、顯示字節(jié)點(diǎn)陣 屏幕控制命令：6、清屏，7、上移，8、下移、9、左移、10、右移（3）命

3、令幀 顯示國(guó)標(biāo)漢字 命令格式：F0 XX YY QQ WW XX:為以漢字為單位的屏幕行坐標(biāo)值，取值范圍00到07。 YY:為以漢字為單位的屏幕列坐標(biāo)值，取值范圍00到01。 QQ WW：坐標(biāo)位置上要顯示的GB2310漢字區(qū)位碼。4其它未盡內(nèi)容請(qǐng)參見(jiàn)實(shí)驗(yàn)指導(dǎo)書(shū)（P188-P200）實(shí)驗(yàn)內(nèi)容與要求1.設(shè)計(jì)一個(gè)液晶顯示驅(qū)動(dòng)電路，要求能夠顯示兩行不少于14個(gè)字的漢字字符，且具有清屏、左移、上移功能。顯示內(nèi)容自定。（6分）2.設(shè)計(jì)一個(gè)液晶顯示驅(qū)動(dòng)電路，要求能夠顯示至少兩個(gè)周期的三角波形，并顯示“T=30mS”的字樣。（4分）3.在上述2的基礎(chǔ)上增加顯示方波的功能，且可通過(guò)按鍵實(shí)現(xiàn)三角波和方波的切換顯示

4、（3）。1.library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity zjf1 is port(clk: in std_logic; clear: in std_logic; -清零命令 left: in std_logic; -左移命令 right: in std_logic; -右移命令 busy: in std_logic; -忙信號(hào)標(biāo)志 data : out std_logic_vector(7 downto 0); -

5、8位數(shù)據(jù)輸出 req : out std_logic); -請(qǐng)求信號(hào) end entity zjf1; architecture art of zjf1 is signal s:std_logic_vector(31 downto 0); -漢字高位和低位的區(qū)位碼 signal n:std_logic_vector(3 downto 0); -顯示十六個(gè)漢字的選擇信號(hào) signal count:std_logic_vector(2 downto 0); -五個(gè)字節(jié)命令的計(jì)數(shù)器 signal sel:std_logic; -顯示十六個(gè)漢字的進(jìn)位時(shí)鐘信號(hào) signal gateclock:std_

6、logic; -5個(gè)字節(jié)命令的計(jì)數(shù)器時(shí)鐘信號(hào) signal scanclk:std_logic; -分頻時(shí)鐘信號(hào) begin process(clk,scanclk) variable scan: std_logic_vector(20 downto 0); -分頻進(jìn)程 begin if clk'event and clk='1' then if scan="111111111111111111111" then scan:="000000000000000000000" else scan:=scan+1; end if; en

7、d if; scanclk<=scan(3); end process; process(gateclock) -5個(gè)字節(jié)計(jì)數(shù)器的進(jìn)程 begin if gateclock'event and gateclock='1' then if count="100" then count<="000" else count<=count+1; end if; end if; end process; process (scanclk) is begin if rising_edge(scanclk) then if b

8、usy = '0' then if clear = '1' then data<=x"f4" elsif right='1' then data<=x"f5" elsif left='1' then data<=x"f7" else case count is when "000"=>data<=x"f0" sel<='0' when "001"=>dat

9、a<=s(31 downto 24); when "010"=>data<=s(23 downto 16);sel<='1' when "011"=>data<=s(15 downto 8); when "100"=>data<=s(7 downto 0); when others=>null; end case; end if; gateclock<='1' ELSE gateclock<='0' end if; end

10、 if; end process; req<='1' when gateclock='1' else '0' process(sel) begin if sel'event and sel='0' then n<=n+1; case n is when "0000"=> s<=x"00003416" -分別是"xx,yy,qq,ww" when "0001"=> s<=x"0100292F"

11、; when "0010"=> s<=x"02001A0E" when "0011"=> s<=x"0300291D" when "0100"=> s<=x"04002A0F" when "0101"=> s<=x"05001E16" when "0110"=> s<=x"06003011" when "0111"=&

12、gt; s<=x"07001625" when "1000"=> s<=x"00011037" when "1001"=> s<=x"01013426" when "1010"=> s<=x"0201294E" when "1011"=> s<=x"03011406" when "1100"=> s<=x"04013330

13、" when "1101"=> s<=x"0501282B" when "1110"=> s<=x"06011C32" when "1111"=> s<=x"07012421" when others=>null; end case; end if; end process; end architecture; 2.library ieee;use ieee.std_logic_1164.all;use ieee.std_l

14、ogic_unsigned.all;entity zjf2 is port(clock,busy:in std_logic; req:out std_logic; DATE:out std_logic_vector(7 to 0);end entity zjf2 ;architecture art of zjf2 issignal r: std_logic;signal db,db3,db4: std_logic_vector(7 to 0);signal js:std_logic_vector(3 downto 0);signal n: std_logic_vector(10 to 0);s

15、ignal b,clk1,clk2:std_logic;signal XX,YY:std_logic_vector(7 downto 0);signal sl:std_logic_vector(2 downto 0); begin req<=r; DATE<=db; process(clock) is begin if clock'event and clock='1' then if busy='0' then r<='1' else r<='0' case sl is when "00

16、0"=> db<=X"F2" clk1<='1' when "001"=> db<=XX; clk1<='0' when "010"=> db<=YY; when "011"=> db<=X"F1" clk2<='1' when "100"=> db<=db3; clk2<='0' when "101"

17、;=> db<=X"17"-列 when "110"=> db<=db4; when others =>null; end case; if sl="110" then sl<="000" else sl<=sl+1; end if; end if; end if; end process;process(clk1)-三角波 begin if clk1'event and clk1='1' then -127進(jìn)制 if XX=X"7F&qu

18、ot; then-7f XX<=X"00" else XX<=XX+1; end if; if b='0' then -79進(jìn)制 if YY=X"1F" then-1f b<='1' else YY<=YY+1; end if; elsif b='1' then if YY=X"00" then b<='0' else YY<=YY-1; end if; end if; end if; end process;process(clk2)-字符顯示 begin if clk2'event and clk2='1' then if js="1011" then js<="0000" else js<=js+1; end if; case js is when "0000"=> db3<=X"05" when "0001"