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1、M95256M95128256Kbit and 128Kbit Serial SPI Bus EEPROMWith High Speed ClockFEATURES SUMMARYCompatible with SPI Bus Serial Interface (Positive Clock SPI ModesSingle Supply Voltage:4.5 to 5.5V for M95xxx2.5 to 5.5V for M95xxx-W1.8 to 5.5V for M95xxx-RHigh Speed10MHz Clock Rate, 5ms Write TimeStatus Reg
2、isterHardware Protection of the Status RegisterBYTE and PAGE WRITE (up to 64 BytesSelf-Timed Programming CycleAdjustable Size Read-Only EEPROM AreaEnhanced ESD ProtectionMore than 100000 Erase/Write CyclesMore than 40-Year Data RetentionTable 1. Product List ReferencePart NumberM95256M95256M95256-W
3、M95256-R M95128M95128M95128-W M95128-ROctober 20041/39M95256, M95128TABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Table 1.Figure 1.Figure 2.Figure 3.Table 2.Product List . . . . . . . . . .
4、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
5、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6、 . .5SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Serial Data Output (Q. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Serial Data I
7、nput (D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Serial Clock (C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Chip Select (S . . . . .
8、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Hold (HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Write Protect (W. . . . . . . . . .
9、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6CONNECTING TO THE SPI BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 4.Bus Master and Memory Devices on the SPI Bus. . .
10、 . . . . . . . . . . . . . . . . . . . . . . . . . . . .7SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 5.SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11、. . . . . . . . . . . . . . . . . .8OPERATING FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12、 . . . . . . . . . .9Power On Reset: VCC Lock-Out Write Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Active Power an
13、d Standby Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 6.Hold Condition Activation. . . . . . . .
14、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 3.Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . .
17、. . . . . . . . . . . . . . . . . . . . . . . . .10Data Protection and Protocol Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 4.Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18、 . . .10MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 7.Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11INSTRUCTIONS . . . .
19、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 5.Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Write Enable (WREN . . . . . . . .
20、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Figure 8.Write Enable (WREN Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132/39M95256, M95128Write Disable (WRDI. . . . . . . . . . . . . . . . . . . .
21、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Figure 9.Write Disable (WRDI Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Read Status Register (RDSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22、. . . . . . . . . . . . . . . . .14WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23、 . . . . . . . . . . . . . . . .14BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24、 . . . . . . . . . . . .14Figure 10.Read Status Register (RDSR Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Write Status Register (WRSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 6.Protection Modes.
25、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 11.Write Status Register (WRSR Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Read from Memory Array (READ . . . . . . . . . . . . . . . . . . . . .
26、. . . . . . . . . . . . . . . . . . . . . . . . . . .17Figure 12.Read from Memory Array (READ Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Write to Memory Array (WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Fi
27、gure 13.Byte Write (WRITE Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 14.Page Write (WRITE Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19POWER-UP AND DELIVERY STATE. . . . . . . . . . . . .
28、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 7.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30、 . . . . . . . . . . . . . .21DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 8.Operating Conditions (M95xxx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 9.Op
31、erating Conditions (M95xxx-W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 10.Operating Conditions (M95xxx-R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 11.AC Measurement Conditions. . . . . . . . . . . . . . .
32、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Figure 15.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 12.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33、. . . . . . . . . . . . .23Table 13.DC Characteristics (M95xxx, Device Grade 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 14.DC Characteristics (M95xxx, Device Grade 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 15.DC Characteristics (M95xxx-W,
34、Device Grade 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 16.DC Characteristics (M95xxx-W, Device Grade 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Table 17.DC Characteristics (M95xxx-R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35、. . . . . . .25Table 18.AC Characteristics (M95xxx, Device Grade 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 19.AC Characteristics (M95xxx, Device Grade 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Table 20.AC Characteristics (M95xxx-W, Device Grade
36、 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 21.AC Characteristics (M95xxx-W, Device Grade 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Table 22.AC Characteristics (M95xxx-R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37、. .30Figure 16.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Figure 17.Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Figure 18.Output T
38、iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333/39M95256, M95128Figure 19.PDIP8 8 pin Pla
39、stic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . .33Table 23.PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . .33Figure 20.SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . .34Table 24.SO8 narrow 8 lead
40、 Plastic Small Outline, 150 mils body width, Package Mechanical Data34Figure 21.SO8 wide 8 lead Plastic Small Outline, 200 mils body width, Package Outline. . . . . .35Table 25.SO8 wide 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data35Figure 22.TSSOP8 8 lead Thin Shrink Sm
41、all Outline, Package Outline . . . . . . . . . . . . . . . . . . .36Table 26.TSSOP8 8 lead Thin Shrink Small Outline, Package Mechanical Data. . . . . . . . . . . .36PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42、 . . .37Table 27.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38Table 28.Document Rev
43、ision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384/39M95256, M95128SUMMARY DESCRIPTIONThese electrically erasable programmable memo-ry (EEPROM devices are accessed by a highspeed SPI-compatible bus. The memory array isorganized as 32768 x 8
44、bit (M95256 and 16384 x8 bit (M95128.The device is accessed by a simple serial interfacethat is SPI-compatible. The bus signals are C, Dand Q, as shown in Table 2. and Figure 2.The device is selected when Chip Select (S is tak-en Low. Communications with the device can beinterrupted using Hold (HOLD
45、. sions, and how to identify pin-1.Table 2. Signal NamesClock D QSerial Data InputSerial Data OutputChip SelectProtect V CCSupply VoltageGroundV SS5/39M95256, M95128SIGNAL DESCRIPTIONDuring all operations, VCC must be held stable andwithin the specified valid range: VCC (min toV CC (max.All of the i
46、nput and output signals must be heldHigh or Low (according to voltages of VIH , VOH , VIL or VOL , as specified in Table 13. to Table 17. These signals are described next.Serial Data Output (Q.This output signal isused to transfer data serially out of the device.Data is shifted out on the falling ed
47、ge of SerialClock (C.Serial Data Input (D.This input signal is used totransfer data serially into the device. It receives in-structions, addresses, and the data to be written.Values are latched on the rising edge of SerialClock (C.Serial Clock (C.This input signal provides thetiming of the serial in
48、terface. Instructions, address-es, or data present at Serial Data Input (D arelatched on the rising edge of Serial Clock (C. Dataon Serial Data Output (Q changes after the fallingedge of Serial Clock (C.When this input signal is High,the device is deselected and Serial Data Output(Q is at high imped
49、ance. Unless an internal Writecycle is in progress, the device will be in the Stand-lects the device, placing it in the Active Powermode.is required prior to the start of any instruction. pause any serial communications with the devicewithout deselecting the device.During the Hold condition, the Ser
50、ial Data Output(Q is high impedance, and Serial Data Input (Dand Serial Clock (C are Dont Care.To start the Hold condition, the device must be se-The main purpose of this in-put signal is to freeze the size of the area of mem-ory that is protected against Write instructions (asspecified by the value
51、s in the BP1 and BP0 bits ofthe Status Register.This pin must be driven either High or Low, andmust be stable during all write instructions.6/39M95256, M95128CONNECTING TO THE SPI BUSThese devices are fully compatible with the SPIprotocol.All instructions, addresses and input data bytesare shifted i
52、n to the device, most significant bitfirst. The Serial Data Input (D is sampled on thefirst rising edge of the Serial Clock (C after ChipAll output data bytes are shifted out of the device,most significant bit first. The Serial Data Output(Q is latched on the first falling edge of the SerialClock (C
53、 after the instruction (such as the Readfrom Memory Array and Read Status Register in-structions have been clocked into the device.Figure 4. shows three devices, connected to anMCU, on a SPI bus. Only one device is selected ata time, so only one device drives the Serial DataOutput (Q line at a time,
54、 all the others being highimpedance. 7/39M95256, M95128SPI ModesThese devices can be driven by a microcontrollerwith its SPI peripheral running in either of the twofollowing modes:CPOL=0, CPHA=0CPOL=1, CPHA=1For these two modes, input data is latched in onthe rising edge of Serial Clock (C, and outp
55、ut datais available from the falling edge of Serial Clock(C.The difference between the two modes, as shownin Figure 5., is the clock polarity when the busmaster is in Stand-by mode and not transferringdata:C remains at 0 for (CPOL=0, CPHA=0C remains at 1 for (CPOL=1, CPHA=1 8/39M95256, M95128OPERATI
56、NG FEATURESPower-upWhen the power supply is turned on, VCC risesfrom VSS to VCC .lowed to follow the VCC voltage. It must not be al-lowed to float, but should be connected to VCC viaa suitable pull-up resistor.sensitive as well as level sensitive. After Power-up, the device does not become selected
57、until afalling edge has first been detected on Chip Selectbeen High, prior to going Low to start the first op-eration.Power On Reset: VCC Lock-Out Write ProtectIn order to prevent data corruption and inadvertentWrite instructions during Power-up, a Power OnReset (POR circuit is included. The interna
58、l resetis held active until VCC has reached the Power OnReset (POR threshold voltage, and all operationsare disabled the device will not respond to anyinstruction. In the same way, when VCC drops fromthe operating voltage, below the Power On Reset(POR threshold voltage, all operations are dis-abled
59、and the device will not respond to any in-struction.At Power-down, the device must be deselected.voltage applied on VCC .Active Power and Standby Power Modesed, and in the Active Power mode. The deviceconsumes ICC , as specified in Table 13. to Table 17. .lected. If an Erase/Write cycle is not currently inprogress, the device then goes in
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