pwm控制直流電機(jī)_verilog_l9110

1、modulepwm(clk,en,speed,dir_in,pwm1,pwm2);inputclk;inputen;input2:0speed;inputdir_in;outputpwm1;outputpwm2;/regdir_out1;/regdir_out2;/regpwm_signal;wirew_dir1,w_dir2;counteru1(.clk(clk),.en_dir1(w_dir1),.en_dir2(w_dir2),.speed(speed),.out1(pwm1),.out2(pwm2);directionu2(.clk(clk),.dir_in(dir_in),.dir_

2、out1(w_dir1),.dir_out2(w_dir2);endmodulemodulecounter(clk,en_dir1,en_dir2,speed,out1,out2);inputclk;/系統(tǒng)時(shí)鐘inputen_dir1;inputen_dir2;input2:0speed;/正轉(zhuǎn)使能端/反轉(zhuǎn)使能端/速度調(diào)節(jié)，3個(gè)檔，100最快outputout1;outputout2;/輸出正轉(zhuǎn)/輸出反轉(zhuǎn)regout1;regout2;reg6:0cnt;/計(jì)數(shù)，用來產(chǎn)生波形always(posedgeclk)beginif(cnt7d100)cnt=cnt+7b1;elsecnt=7b0;e

3、ndalways(posedgeclk)beginif(en_dir1)if(speed=3b100)if(cnt7d10)out1=1b0;elseout1=1b1;elseif(speed=3b010)if(cnt7d80)/40)out1=1b0;else/3檔，占空比90%/2檔，占空比60%out1=1b1;elseif(speed!=3b000)/1檔，占空比30%(實(shí)際上操作條件為“只要不等于000，就執(zhí)行30%占空比”，擋位間能平滑過渡)if(cnt7d95)/70)out1=1b0;elseout1=1b1;elseout1=1b0;else/檔位為0，輸出0out1=1b0

4、;endalways(posedgeclk)beginif(en_dir2)if(speed=3b100)if(cnt7d10)out2=1b0;else/3檔，占空比90%out2=1b1;elseif(speed=3b010)/2檔，占空比20%if(cnt7d80)/40)out2=1b0;elseout2=1b1;elseif(speed!=3b000)/1檔，占空比5%(實(shí)際上操作條件為“只要不等于000，就執(zhí)行5%占空比”，擋位間能平滑過渡)if(cnt7d95)/70)out2=1b0;elseout2=1b1;elseout2=1b0;elseout2=1b0;endendmodule/檔位為0，輸出0moduledirection(clk,/方向控制模塊，用來決定正轉(zhuǎn)還是反轉(zhuǎn)dir_in,dir_out1,dir_out2);inputclk;inputdir_in;outputdir_out1;/dir_out1=1，dir_out2=0時(shí)，正轉(zhuǎn)；反之則反轉(zhuǎn)outputdir_out2;regdir_out1;regdir_out2;always(posedgeclk)beginif(dir_in)/控制信號為1時(shí)，正轉(zhuǎn)begindir_out1=1b1;d