基于CPLD的三相多波形函數(shù)發(fā)生器(共51頁)

1、 基于CPLD的三相(sn xin)多波形函數(shù)發(fā)生器The Design of Three Phase MultiSignal Generator Based on CPLD摘 要直接數(shù)字頻率合成(Direct Digital Synthesis，DDS)是20世紀60年代末出現(xiàn)的第三代頻率合成技術(shù)，該技術(shù)從相位概念出發(fā)，以時域采樣定理為基礎(chǔ)，在時域中進行頻率合成，它以可編程邏輯器件(CPLD)作為控制及數(shù)據(jù)處理的核心，可將波形(b xn)數(shù)據(jù)用D/A轉(zhuǎn)換器快速恢復(fù)?；?jy)CPLD和DDS技術(shù)的函數(shù)發(fā)生器可以實現(xiàn)信號波形的多樣化，同時大大提高輸出信號的帶寬。整個設(shè)計采用MAX+ plus

2、 II開發(fā)平臺，VHDL編程實現(xiàn)，基于可編程邏輯器件CPLD設(shè)計多波形信號發(fā)生器。用VHDL編程實現(xiàn)，其設(shè)計過程簡單，極易修改，可移植性強。系統(tǒng)以CPLD為核心，采用直接數(shù)字合成技術(shù)，輔以必要的模擬電路，構(gòu)成一個波形穩(wěn)定，精度較高的函數(shù)信號發(fā)生器。系統(tǒng)的特色在于除晶體振蕩器和A/D轉(zhuǎn)換外，全部集成在一片CPLD芯片上，使系統(tǒng)大大簡化。它可輸出頻率、幅度可調(diào)的正弦波、三角波、方波。另外由于CPLD具有可編程重置特性，因而可以方便地更換波形數(shù)據(jù)，且簡單易行，帶來極大方便。 關(guān)鍵詞：信號發(fā)生器設(shè)計；三相；VHDL；CPLD；MAX+ plus IIABSTRACTDirect digital fre

3、quency synthesize(DDFS) is a recently and rapidly developed technology which features high frequency resolutionThis paper briefly introduces the basic principle of DDS. The basic principle and performance of CPLD chipThen it mainly describes how to use CPLD chip to design a function generator of hig

4、h accuracyThe principle of three-phase multi-signal generator based on CPLD and DDS technology is introducedBased on these，the modules of CPLD design are givenThe multi-wave signal generator is designed based on program-mable logical component CPLDThe VHDL programming realization and the MAX+ plus I

5、I development platform. Besides the crystal oscillator and the A/D transformation，the entire system completely integrates on the CPLD chipThe multi-wave signal generator may output the sine-wave，the triangle-wave，the square-waveThen downloaded under the situation which the entire system hardware con

6、nects do not change，and finally output the special profile which user needsThe multi-wave signal generator generates wave which the conventional function signal generators cant makeMoreover because of the programmable reset feature of the CPLD，the generator can change the wave data conveniently and

7、practice easilyThe whole design realizes by the VHDL programmerIts design process has simple feature，easy modification and high transportationKeywords：Signal Generator Design；Three-phase；VHDL；CPLD；MAX+ plus II目 錄 TOC o 1-4 u 1 引 言 PAGEREF _Toc170015742 h 12基于(jy)CPLD的三相多波形(b xn)函數(shù)發(fā)生器設(shè)計 PAGEREF _Toc1

8、70015743 h 32.1 波形發(fā)生器系統(tǒng)(xtng)的設(shè)計方法及其技術(shù)指標 PAGEREF _Toc170015744 h 32.1.1設(shè)計方式概述 PAGEREF _Toc170015745 h 32.1.2 三相函數(shù)多波形發(fā)生器技術(shù)指標 PAGEREF _Toc170015746 h 52.1.3三相波形發(fā)生器設(shè)計方法概述 PAGEREF _Toc170015747 h 52.2 設(shè)計方案 PAGEREF _Toc170015748 h 62.2.1 三相函數(shù)發(fā)生器設(shè)計原理 PAGEREF _Toc170015749 h 62.2.2 多波形發(fā)生器的各個波形模塊設(shè)計方式簡介 PAGE

9、REF _Toc170015750 h 102.3 調(diào)試部分 PAGEREF _Toc170015751 h 122.3.1 CPLD在使用中遇到的問題 PAGEREF _Toc170015752 h 122.3.2 控制電路的調(diào)試 PAGEREF _Toc170015753 h 132.3.3 DAC電路的調(diào)試 PAGEREF _Toc170015754 h 132.3.4 程序的調(diào)試 PAGEREF _Toc170015755 h 132.3.5 硬件電路的調(diào)試 PAGEREF _Toc170015756 h 14結(jié) 論 PAGEREF _Toc170015757 h 16參考文獻 PAG

10、EREF _Toc170015758 h 17附錄(fl)1 三相多波形函數(shù)發(fā)生器各模塊(m kui)的程序 PAGEREF _Toc170015759 h 18附錄(fl)2 元件介紹 PAGEREF _Toc170015760 h 241 DAC0832 PAGEREF _Toc170015761 h 242 LM324 PAGEREF _Toc170015762 h 253 PM7128SLC84-15芯片 PAGEREF _Toc170015763 h 26附錄3電路原理圖 PAGEREF _Toc170015764 h 27附錄4 英文資料及譯文 PAGEREF _Toc170015

11、765 h 281英文資料 PAGEREF _Toc170015766 h 282英文譯文 PAGEREF _Toc170015767 h 37致 謝 PAGEREF _Toc170015768 h 44PAGE PAGE 501 引 言現(xiàn)代電子技術(shù)的核心技術(shù)是EDA（Electronic Design Automation）。EDA技術(shù)就是依賴強大的電子計算機在EDA開發(fā)平臺上，對硬件描述語言HDL(Hardware Description Language)系統(tǒng)邏輯描述手段完成的設(shè)計文件，自動的完成邏輯編譯、邏輯化簡、邏輯分割、邏輯綜合、結(jié)構(gòu)綜合（布局布線），以及邏輯優(yōu)化和仿真測試，直至(

12、zhzh)實現(xiàn)既定的電子線路系統(tǒng)功能。EDA技術(shù)使得設(shè)計者的工作僅限于利用軟件的方式，即利用硬件描述語言和EDA軟件來完成對系統(tǒng)硬件功能的實現(xiàn)。EDA使得電子(dinz)技術(shù)領(lǐng)域各學(xué)科的界限更加模糊，更加護為包容：模擬與數(shù)字、軟件與硬件、系統(tǒng)與器件、行為與結(jié)構(gòu)、ASIC（Application Specific Integrated Circuit,專用集成電路）與FPGA（Field Programmable Gate Array）等。EDA技術(shù)(jsh)在21世紀得到的很大進步，例如更大規(guī)模的FPGA和CPLD（Complex Programmable Logic Device）器件的不斷

13、推出；軟硬件IP核(Intellectual Property)在電子行業(yè)的產(chǎn)業(yè)領(lǐng)域、技術(shù)領(lǐng)域和設(shè)計應(yīng)用領(lǐng)域得到進一步的確認；系統(tǒng)級、行為驗證級硬件描述語言(System C)的出現(xiàn)，使復(fù)雜電子系統(tǒng)和驗證趨于簡單。硬件描述語言VHDL全名是VHSIC(Very High Speed Integrated Circuit) Hardware Description Language是EDA技術(shù)的重要組成部分,由美國國防部發(fā)起創(chuàng)建，由IEEE (The Institute of Electrical and Electronics Engineers)進一步發(fā)展并發(fā)布，是硬件描述語言的業(yè)界標準之一

14、。VHDL語言具有很強的電路描述和建模能力，能從多個層次對數(shù)字系統(tǒng)進行建模和描述，從而大大簡化了硬件設(shè)計任務(wù)，提高了設(shè)計效率和可靠性。VHDL具有與具體硬件電路無關(guān)和與設(shè)計平臺無關(guān)的特性，并且具有良好的電路行為描述和系統(tǒng)描述的能力，VHDL支持各種模式的設(shè)計方法：自頂向下與自頂向上或混合方法，在面對當今電子產(chǎn)品生命周期縮短，需要多次重新設(shè)計以融入最新技術(shù)、改變工藝等方面，VHDL具有良好的適應(yīng)性。向器件作編程或適配習慣上叫做下載，這要通過下載軟件平臺或者下載電纜實現(xiàn)。這是設(shè)計過程中的重要步驟，可以利用MAX+PLUS軟件在計算機上完成設(shè)計并下載到目標器件中。EDA工具軟件大致可以分為5個模塊：

15、設(shè)計輸入編輯器，仿真器，HDL綜合器，適配器，下載器等。Direct Digital Synthesis(DDS)是20世紀60年代末出現(xiàn)的第三代頻率合成技術(shù)。該技術(shù)從相位概念出發(fā)，以時域采樣定理為基礎(chǔ)(jch)，在時域中進行頻率合成，它以可編程邏輯器件(CPLD)作為控制及數(shù)據(jù)處理的核心，將存于Flash ROM的波形數(shù)據(jù)用D/A轉(zhuǎn)換器快速恢復(fù)。DDS頻率轉(zhuǎn)換速度快，頻率分辨率高，并在頻率轉(zhuǎn)換時可保持相位的連續(xù)，因而易于實現(xiàn)多種調(diào)制功能。DDS是全數(shù)字化技術(shù)，其幅度、相位、頻率均可實現(xiàn)程控，并可通過更換波形數(shù)據(jù)靈活實現(xiàn)任意波形。此外，DDS易于單片集成，體積小，價格低，功耗小，因此DDS技術(shù)

16、近年來得到了飛速發(fā)展，其應(yīng)用也越來越廣泛(gungfn)?；贑PLD和DDS技術(shù)的函數(shù)發(fā)生器可以實現(xiàn)信號波形的多樣化，而且方便可靠，簡單經(jīng)濟，系統(tǒng)易于擴展，同時可大大提高輸出信號的帶寬。CPLD為連續(xù)式互連結(jié)構(gòu)，器件引腳到內(nèi)部邏輯單元，以及各邏輯單元之間，是通過全局互連總線中的多路選擇器或交叉矩陣選通構(gòu)成信號通路。其主要特點是內(nèi)部時間延時與器件邏輯結(jié)構(gòu)等無關(guān)，各模塊之間提供了具有固定時延的快速互連通道，因此可以預(yù)測時間延時，容易消除競爭(jngzhng)冒險等現(xiàn)象，便于各種邏輯電路設(shè)計。 本文的DDS系統(tǒng)以CPLD為核心，采用直接數(shù)字合成技術(shù)，輔以必要的模擬電路，構(gòu)成一個波形穩(wěn)定，精度較高的

17、函數(shù)信號發(fā)生器。本系統(tǒng)的特色在于CPLD中集成了大部分電路，使系統(tǒng)大大簡化，除輸出所需的正弦波、方波、三角波，還可進行波形存儲,三種波形之間的相位差均為120，是三相的CPLD系統(tǒng)。DDS的理論依據(jù)是奈奎斯特抽樣定理。根據(jù)該定理，對于一個周期正弦波連續(xù)信號，可以沿其相位軸方向，以等量的相位間隔對其進行相位/幅度抽樣，得到一個周期性的正弦信號的離散相位的幅度序列，并且對模擬幅度進行量化，量化后的幅值采用相應(yīng)的二進制數(shù)據(jù)編碼。這樣就把一個周期的正弦波連續(xù)信號轉(zhuǎn)換成為一系列離散的二進制數(shù)字量，然后通過一定的手段固化在只讀存儲器ROM 中，每個存儲單元的地址即是相位取樣地址，存儲單元的內(nèi)容是已經(jīng)量化了

18、的正弦波幅值。這樣的一個只讀存儲器就構(gòu)成了一個與2周期內(nèi)相位取樣相對應(yīng)的正弦函數(shù)表，因它存儲的是一個周期的正弦波波形幅值，因此又稱其為正弦波形存儲器。此時，正弦波形信號的相位與時間成線性關(guān)系。根據(jù)這一基本關(guān)系，在一定頻率的時鐘信號作用下，通過一個線性的計數(shù)時序發(fā)生器所產(chǎn)生的取樣地址對已得到的正弦波波形存儲器進行掃描，進而周期性地讀取波形存儲器中的數(shù)據(jù)，其輸出通過數(shù)模轉(zhuǎn)換器及低通濾波器就可以合成一個完整的、具有一定頻率的正弦波信號。DDS電路一般包括系統(tǒng)時鐘、相位累加器、相位調(diào)制器、ROM 查找表、D/A轉(zhuǎn)換器和低通濾波器(LPF)。基于(jy)CPLD和DDS技術(shù)的函數(shù)發(fā)生器可以實現(xiàn)信號波形的

19、多樣化，而且方便可靠，簡單經(jīng)濟，系統(tǒng)易于擴展，同時可大大提高輸出信號的帶寬。2基于CPLD的三相多波形函數(shù)(hnsh)發(fā)生器設(shè)計2.1 波形發(fā)生器系統(tǒng)的設(shè)計(shj)方法及其技術(shù)指標2.1.1設(shè)計(shj)方式概述在電子工程設(shè)計與測試中，常常需要一些具有特殊要求的信號，要求其波形產(chǎn)生多，頻率方便可調(diào)。通常的信號產(chǎn)生器難以滿足要求，市場(shchng)上出售的任意信號產(chǎn)生器價格昂貴。在老師指導(dǎo)下，結(jié)合實際要求，我設(shè)計了一種基于CPLD的三相多波形函數(shù)發(fā)生器，能輸出正弦波、三角波、方波等波形信號，波形信號之間的相位差均為120。復(fù)雜可編程邏輯器件CPLD器件可以代替許多分立元器件，從而大大降低了電

20、路板的復(fù)雜程度。對于CPLD器件的設(shè)計一般可以分為設(shè)計輸入、設(shè)計實現(xiàn)和器件編程三個設(shè)計步驟以及相應(yīng)的功能仿真、時序仿真和器件測試三個設(shè)計驗證過程。設(shè)計輸入有多種方式，目前最常用的有電路圖和硬件描述語言兩種，對于簡單的設(shè)計，可采用原理圖的方式設(shè)計，對于復(fù)雜的設(shè)計可使用原理圖或硬件描述語言(Verilog, AHDL, VHDL語言)，或者兩者混用，采用層次化設(shè)計方法，分模塊層次地進行描述。原理圖設(shè)計方法主要是按照數(shù)字系統(tǒng)的功能采用具體的邏輯器件組合來實現(xiàn)的把這些由具體器件實現(xiàn)邏輯功能的電路圖輸入到軟件當中。這種設(shè)計方法比較直觀。 硬件描述語言設(shè)計方法主要把數(shù)字系統(tǒng)的邏輯功能用硬件語言來描述，采用

21、VHDL語言描述的數(shù)字系統(tǒng)大致有三種；其一稱為行為描述，它用幾個包含著若干順序語句的進程描述輸入與輸出之間的轉(zhuǎn)換關(guān)系；其二是數(shù)據(jù)流描述，用一系列的并發(fā)信號賦值語句描述輸入與輸出之間的關(guān)系；其三為結(jié)構(gòu)描述方式，是通過元件之間的互聯(lián)關(guān)系描述輸出電路的結(jié)構(gòu)。無論是原理圖輸入還是描述語言輸入都各有其優(yōu)點，原理圖設(shè)計適合于對器件比較熟悉，元件之間的互聯(lián)清楚，并且需要的設(shè)計比較簡單的情況，而對于器件不熟悉，設(shè)計復(fù)雜的情況來說，使用硬件描述語言要方便一些。設(shè)計實現(xiàn):設(shè)計實現(xiàn)是指從設(shè)計輸入文件到熔絲圖文件(CPLD)的編譯過程。在該過程中，編譯軟件自動地對設(shè)計文件進行綜合、優(yōu)化，并針對所選中的器件進行映射、布

22、局、布線、產(chǎn)生相應(yīng)的熔絲圖或位流數(shù)據(jù)文件，在此過程中，由于編譯軟件給系統(tǒng)管腳的分配是比較雜亂的，為了電路板布線的方便，用戶可以對輸入/輸出管腳進行管腳鎖定。器件編程:器件編程就是將熔絲圖文件或位流數(shù)據(jù)文件下載到相應(yīng)的CPLD器件中，并與CPLD器件的管腳相對應(yīng)，所用(su yn)的軟件是ALTARE公司提供的CPLDDN4，這是ALTARE公司CPLD系列的專用下載軟件。設(shè)計校驗:對應(yīng)于設(shè)計輸入、設(shè)計實現(xiàn)(shxin)和器件編程，設(shè)計驗證分為了功能仿真、時序仿真、器件測試三個部分。功能仿真驗證設(shè)計的邏輯功能，在設(shè)計輸入過程中，對部分功能或整個設(shè)計均可進行仿真；時序仿真是在設(shè)計實現(xiàn)以后，針對器件

23、的布局、布線方案進行時延仿真，分析定時關(guān)系:器件測試是在器件編程后，通過實驗或借助(jizh)測試工具，測試器件最終的功能和性能指標。在設(shè)計中系統(tǒng)的接口電路、信號源的大多數(shù)邏輯控制都在CPLD中實現(xiàn)。在該流程中仿真是重點。仿真又可分為功能仿真(前仿真)與時序仿真(后仿真)。根據(jù)電路設(shè)計編制仿真文件，在文件被綜合前進行仿真，可驗證電路功能；在保證電路已實現(xiàn)設(shè)計的功能后，進行綜合并對綜合的結(jié)果進行時序仿真，可驗證電路的時序是否滿足要求。當電路的前仿真與后仿真都滿足要求，則電路的設(shè)計是成功的。然后設(shè)置器件類型并進行引腳鎖定，再對文件進行適合于所加配置的邏輯綜合；通過后即完成設(shè)計。最后結(jié)合系統(tǒng)中的其它

24、部分進行連調(diào)，如發(fā)現(xiàn)問題可修改設(shè)計。本設(shè)計中使用了ALTERA公司提供的配套軟件MAX+PLUSII進行文件的輸入、編譯和下載。MAX+PLUSII的軟件設(shè)計主要由設(shè)計輸入、項目編譯、項目校驗和器件編程等四部分構(gòu)成。設(shè)計輸入功能仿真編譯實現(xiàn)時序仿真編程下載調(diào)試結(jié)束圖2.1-1 CPLD設(shè)計(shj)流程圖設(shè)計輸入MUS+PLUS文本編輯器MUS+PLUS圖形編輯器項目編譯編譯器網(wǎng)表提取器數(shù)據(jù)庫建庫器適配綜合器器件編程MUS+PLUS編程器項目校驗MUS+PLUS時間分析器MUS+PLUS圖2.1-2 MUS+PLUS設(shè)計(shj)的主要組成部分2.1.2 三相(sn xin)函數(shù)多波形發(fā)生器技

25、術(shù)指標三種波形之間的相位差均為120，可以同時輸出，具有三相的功能。對以下三種波形的頻率均要求：產(chǎn)生的頻率都可以預(yù)置；輸出的信號幅值能在100mv3V的范圍內(nèi)調(diào)整。對正弦波信號的要求為：信號頻率范圍：20Hz-20kHz之間可調(diào)，步長為10Hz；非線性失真系數(shù)3%。對方波信號的要求是：信號頻率范圍：20Hz-20kHz；上升和下降時間qqqqqqqqqqnull; end case; end process;end chu_arc;LIBRARY ieee ; 分頻(fn pn)模塊use ieee.std_logic_1164.all;entity fana is port(a:in int

26、eger range 0 to 312; clk:in std_logic; q:out std_logic);end fana;architecture fan_arc of fana isbegin process(clk) variable b,d:std_logic; variable c:integer range 0 to 312; begin if clkevent and clk=1then if b=0then c:=a-1; b:=1; else if c=1 then b:=0; d:=not d; else c:=c-1; end if; end if; end if;

27、 q=d; end process;end fan_arc;LIBRARY ieee; 方波模塊(m kui)use ieee.std_logic_1164.all;entity square is port(clk,clr:in std_logic; q:out integer range 0 to 255);end square;architecture sq_arc of square issignal a:bit;begin process(clk,clr) variable cnt:integer; begin if clr=0then a=0; elsif clkevent and

28、 clk=1then if cnt7 then cnt:=cnt+1; else cnt:=0; a=not a; end if; end if; end process; process(clk,a) begin if clkevent and clk=1then if a=1then q=255; else q=0; end if; end if; end process;end sq_arc;LIBRARY ieee;三角(snjio)波模塊use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity delta i

29、s port(clk,reset:in std_logic; q:out std_logic_vector(7 downto 0);end delta;architecture delta_arc of delta isbegin process(clk,reset) variable tmp:std_logic_vector(7 downto 0); variable a:std_logic; begin if reset=0 then tmp:=00000000; elsif clkevent and clk=1 then if a=0then if tmp=11111000then tm

30、p:=11111111; a:=1; else tmp:=tmp+8; end if; else if tmp=00000111then tmp:=00000000; a:=0; else tmp:=tmp-8; end if; end if; end if; q=tmp; end process; end delta_arc;LIBRARY ieee; 正弦波模塊(m kui)use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity delta is port(clk,reset:in std_logic; q:ou

31、t std_logic_vector(7 downto 0);end delta;architecture delta_arc of delta isbegin process(clk,reset) variable tmp:std_logic_vector(7 downto 0); variable a:std_logic; begin if reset=0 then tmp:=00000000; elsif clkevent and clk=1 then if a=0then if tmp=11111000then tmp:=11111111; a:=1; else tmp:=tmp+8;

32、 end if; else if tmp=00000111then tmp:=00000000; a:=0; else tmp:=tmp-8; end if; end if; end if; qqqqa:=00&dlta+sqra; qa:=00&dlta+sina; qa:=00&sqra+sina; qa:=00&dlta+sqra; b:=a+sina; c:=00&b(9 downto 2); d:=0000&a(9 downto 4); e:=000000&a(9 downto 6); a:=c+d; b:=a+e; qnull; end case; end process;end

33、ch_arc;附錄(fl)2 元件(yunjin)介紹1 DAC0832DAC0832 是一種相當(xingdng)普遍且成本較低的數(shù)/模轉(zhuǎn)換器，該器件(qjin)是一個8位D/A轉(zhuǎn)換器，其轉(zhuǎn)換時間為1s，工作電壓為+5V+15V，基準(jzhn)電壓為10V，它將一個8位的二進制數(shù)轉(zhuǎn)換成模擬電壓，可產(chǎn)生256種不同的電壓值，由于其內(nèi)部有兩個8位寄存器和一個8位D/A轉(zhuǎn)換器，故可進行兩級緩沖操作，使操作有很大的靈活性(本設(shè)計中采用的是單緩沖方式)DAC0832具有以下主要特性：滿足TTL電平規(guī)范的邏輯輸入；分辨率為8位； 建立時間為1us；功耗20mw；是電流型輸出型D/A轉(zhuǎn)換器，在應(yīng)用時外接

34、運放使之成為電壓型輸出。DAC0832的片選地址為7FFFH，當P27有效時，若P0口向其送的數(shù)據(jù)為00H，則U 的輸出電壓為0V；若P0口向其送的數(shù)據(jù)為0FFH時，則的輸出電壓為-5V故當輸出電壓為0V時，Vo：-5V當輸出電壓為-5V時，可得：Vo =+5V，所以輸出波形的電壓變化范圍為-5V +5V連接硬件電路時將兩級寄存器的控制信號并接輸入數(shù)據(jù)，在控制信號作用下直接送入DAC寄存器中。經(jīng)D/A轉(zhuǎn)換和幅度控制，再濾波即可得到波形。圖1 DAC0832內(nèi)部結(jié)構(gòu)如圖所示圖2 DAC08322 LM324LM324四運放是美國(mi u)national公司的產(chǎn)品。LM324是四運放集成電路(

35、jchng-dinl),它采用(ciyng)14腳雙列直插塑料封裝。它的內(nèi)部包含四組形式完全相同的運算放大器, 除電源共用外,四組運放相互獨立。每一組運算放大器可用圖1所示的符號來表示,它有5個引出腳,其中“+”、“-”為兩個信號輸入端,“V+”、“V-”為正、負電源端,“Vo”為輸出端。兩個信號輸入端中,Vi-（-）為反相輸入端,表示運放輸出端Vo的信號與該輸入端的位相反;Vi+（+）為同相輸入端,表示運放輸出端Vo的信號與該輸入端的相位相同。由于LM324四運放電路具有電源電壓范圍寬,靜態(tài)功耗小,可單電源使用,價格低廉等優(yōu)點,因此被廣泛應(yīng)用在各種電路中。 在本系統(tǒng)中，LM324被作為放大器

36、和濾波器來使用。它可以選出各個不同頻段的信號,指示出信號幅度的大小，對信號進行放大后再輸出，提供給使用者需要的波形信號。圖3 LM324管腳圖3 PM7128SLC84-15芯片(xn pin) EPM7128S84-15是CPLD芯片(xn pin)，有128個宏單元、2500個等效(dn xio)邏輯門、15ns的速度、PLCC84封裝形式。除電源引腳、地線引腳、全局控制引腳和JTAG引腳外，共提供了64個可用I/O腳，這些引腳可以任意配置為輸入、輸出和雙向方式。該器件的特點如下:是 一 種高性能的CM0SE EPROM器件。器 件 可通過JTAG接口實現(xiàn)在線編程。內(nèi) 置JTAG BST電

37、路?？?編 程宏單元觸發(fā)器具有專用清除、置位、時鐘和時鐘使能控制。 可 配 置的擴展乘積項分配，允許向每個宏單元提供多達32個乘積項。 圖4EPM7128SLC84-15 附錄(fl)3電路(dinl)原理圖附錄(fl)4 英文資料(zlio)及譯文1英文資料(zlio)(From DIGITAL DESIGN principles & practices ,John F. Wakerly)Language OverviewWhat is VHDL?VHDL is a programming language that has been designed and optimized for d

38、escribing the behavior of digital systems.VHDL has many features appropriate for describing the behavior of electronic components ranging from simple logic gates to complete microprocessors and custom chips. Features of VHDL allow electrical aspects of circuit behavior (such as rise and fall times o

39、f signals, delays through gates, and functional operation) to be precisely described. The resulting VHDL simulation models can then be used as building blocks in larger circuits (using schematics, block diagrams or system-level VHDL descriptions) for the purpose of simulation.VHDL is also a general-

40、purpose programming language: just as high-level programming languages allow complex design concepts to be expressed as computer programs, VHDL allows the behavior of complex electronic circuits to be captured into a design system for automatic circuit synthesis or for system simulation. Like Pascal

41、, C and C+, VHDL includes features useful for structured design techniques, and offers a rich set of control and data representation features. Unlike these other programming languages, VHDL provides features allowing concurrent events to be described. This is important because the hardware described

42、 using VHDL is inherently concurrent in its operation.One of the most important applications of VHDL is to capture the performance specification for a circuit, in the form of what is commonly referred to as a test bench. Test benches are VHDL descriptions of circuit stimuli and corresponding expecte

43、d outputs that verify the behavior of a circuit over time. Test benches should be an integral part of any VHDL project and should be created in tandem with other descriptions of the circuit.A standard languageOne of the most compelling reasons for you to become experienced with and knowledgeable in

44、VHDL is its adoption as a standard in the electronic design community. Using a standard language such as VHDL virtually guarantees that you will not have to throw away and recapture design concepts simply because the design entry method you have chosen is not supported in a newer generation of desig

45、n tools. Using a standard language also means that you are more likely to be able to take advantage of the most up-to-date design tools and that you will have access to a knowledge base of thousands of other engineers, many of whom are solving problems similar to your own.A brief history of VHDLVHDL

46、, which stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language, was developed in the early 1980s as a spin-off of a high-speed integrated circuit research project funded by the U.S. Department of Defense. During the VHSIC program, researchers were confronted with the dau

47、nting task of describing circuits of enormous scale (for their time) and of managing very large circuit design problems that involved multiple teams of engineers. With only gate-level design tools available, it soon became clear that better, more structured design methods and tools would be needed.T

48、o meet this challenge, a team of engineers from three companies ?IBM, Texas Instruments and Intermetrics ?were contracted by the Department of Defense to complete the specification and implementation of a new, language-based design description method. The first publicly available version of VHDL, ve

49、rsion 7.2, was released in 1985. In 1986, the Institute of Electrical and Electronics Engineers, Inc. (IEEE) was presented with a proposal to standardize the language, which it did in 1987 after substantial enhancements and modifications were made by a team of commercial, government and academic rep

50、resentatives. The resulting standard, IEEE 1076-1987, is the basis for virtually every simulation and synthesi product sold today. An enhanced and updated version of the language, IEEE 1076-1993, was released in 1994, and VHDL tool vendors have been responding by adding these new language features t

51、o their products.Although IEEE Standard 1076 defines the complete VHDL language, there are aspects of the language that make it difficult to write completely portable design descriptions (descriptions that can be simulated identically using different vendors?tools). The problem stems from the fact t

52、hat VHDL supports many abstract data types, but it does not address the simple problem of characterizing different signal strengths or commonly used simulation conditions such as unknowns and high-impedance. Soon after IEEE 1076-1987 was adopted, simulator companies began enhancing VHDL with new, no

53、n-standard types to allow their customers to accurately simulate complex electronic circuits. This caused problems because design descriptions entered into one simulator were often incompatible with other simulation environments. VHDL was quickly becoming a nonstandard.To get around the problem of n

54、onstandard data types, another standard was developed by an IEEE committee. This standard, numbered 1164, defines a standard package (a VHDL feature that allows commonly used declarations to be collected into an external library) containing definitions for a standard nine-valued data type. This stan

55、dard data type is called std_logic, and the IEEE 1164 package is often referred to as the Standard Logic package. The IEEE 1076-1987 and IEEE 1164 standards together form the complete VHDL standard in widest use today. (IEEE 1076-1993 is slowly working its way into the VHDL mainstream, but it does n

56、ot add significant new features for synthesis users.)Standard 1076.3(often called the Numeric Standard or Synthesis Standard) defines standard packages and interpretations for VHDL data types as they relate to actual hardware. This standard, which was released at the end of 1995, is intended to repl

57、ace the many custom (nonstandard) packages that vendors of synthesis tools have created and distributed with their products.IEEE Standard 1076.3 does for synthesis users what IEEE 1164 did for simulation users: increase the power of Standard 1076, while at the same time ensuring compatibility betwee

58、n different vendors?tools. The 1076.3 standard includes, among other things:1) A documented hardware interpretation of values belonging to the bit and boolean types defined by IEEE Standard 1076, as well as interpretations of the std_ulogic type defined by IEEE Standard 1164.2) A function that provi

59、des don&care or wild card testing of values based on the std_ulogic type. This is of particular use for synthesis, since it is often helpful to express logic in terms of don抰 care values.3) Definitions for standard signed and unsigned arithmetic data types, along with arithmetic, shift, and type con

60、version operations for those types.The annotation of timing information to a simulation model is an important aspect of accurate digital simulation. The VHDL 1076 standard describes a variety of language features that can be used for timing annotation. However, it does not describe a standard method