SFF-8431簡介及SFI電氣參數(shù)測試課件

1、 SFF-8431簡介及SFI電氣參數(shù)測試 AgendaIntroduction of SFF-8431SFF-8431 Standard Compliance Test of SFIEye Diagram Test by DSA8200Introduction of SFF-8431 BRIEF INTRODUCTION OF SFF-8431The specification of SFF-8431 defines the electrical interfaces and their test methods between the SFP+ module and host board

2、for operation up to 11.1 GBd. The high speed electrical interface between the host and SFP+ module is called “SFI”. SFI simplifies the module and leverages host based transmit pre-emphasis and host based receive equalization to overcome PCB and external media impairments. SFI typically operates with

3、 one connector at the module interface and up to about 200 mm of improved FR4 material or 150 mm of standard FR4. The electrical interface is based on high speed, low voltage AC coupled logic with a nominal differential impedance of 100 . The SFP+ specifications includes management, low speed signal

4、, high speed signal, connector (defined by SFF-8083), mechanical (defined by SFF-8432), and appendices providing parameter and test board definitions, and implementation and measurement descriptions. Introduction of SFF-8431 The SFP+ SUPPORTED STANDARDSIntroduction of SFF-8431 POWER SPECIFICATIONS O

5、F SFP+ The module signal ground contacts VeeR and VeeT should be isolated from module case. At host power up the host shall supply VccT and VccR to the module within 100 ms of each other. SFP+ low speed signaling is based on Low Voltage TTL (LVTTL) operating with a module supply of 3.3 V +/-5% and w

6、ith a host supply range of 2.38 to 3.46 V. To avoid exceeding system power supply limits and cooling capacity, all modules at power up by default shall operate with 1.0 W. Hosts supporting Power Level II operation may enable a Power Level II module through the 2-wire interface. Power Level II module

7、s shall assert the power level declaration bit of SFF-8472. Over long spans such as the 40km Ethernet extended reach (ER) long wavelength applications, the SFP+ transceivers may require additional power consumption, especially at extreme operating conditions. Power Level I modules Up to 1.0 W Power

8、Level II modules Up to 1.5 WGENERAL REQUIREMENTS Introduction of SFF-8431 The maximum power level is allowed to exceed the classified power level for 500 ms following hot insertion or power up, or Power Level II authorization, however the current is limited to values given by the following table. PO

9、WER SPECIFICATIONS OF SFP+Introduction of SFF-8431 The SFP+ module shall meet ESD requirements given in EN61000-4-2, criterion B test specification such that units are subjected to 15 kV air discharges during operation and 8 kV direct contact discharges to the case. Introduction of SFF-8431 HIGH SPE

10、ED ELECTRICAL SPECIFICATIONS of SFISFI signaling is based on differential high speed low voltage logic with AC coupling in the module. SFI was developed with the primary goal of low power and low electromagnetic interference (EMI). To satisfy this requirement the nominal differential signal levels a

11、re 500 mV p-p with edge speed control to reduce EMI.Introduction of SFF-8431 PCB LAYOUT RECOMMENDATIONSThe PCB traces are recommended by the specification to meet 10010 differential impedace with nominal 7% differential coupling. It is preferable to have the impedance tolerance be 5.Route differenti

12、al pairs at least 8x their trace-width from other traces. Avoid sharp angles in routing, chamfer corners.In order to avoid reflection, the recommended minimum trace length requirement is “1 inch” in FR4.When there must be vias on the high-speed differential signals, the 100 differential vias is reco

13、mmended be used. And stubs due to vias must be avoided.The maximum SFI trace length recommend by the specification of SFF-8431.SFF-8431 Standard Compliance Test of SFITEST ENVIRONMENT REQUIREMENTSThe bandwidth of measurement instrument shall be 12 GHz or above;Require AC coupled test equipment on al

14、l test ports；All SFI test equipment must have 50ohm single ended impedance；Reference impedance for differential measurements is 100ohm, and the reference impedance for common mode measurements is 25ohm;Host compliance test board is required. SFF-8431 STANDARD COMPLIANCE TEST of SFITEST METHODOLOGY A

15、ND MEASUREMENT HOST COMPLIANCE TESTA.1 Test point Host system transmitter and receiver compliance are defined by tests in which a Host Compliance Board is inserted in place of the SFP+ module. The compliance points are B.SFF-8431 Standard Compliance Test of SFIA.2 Measurement setupSFF-8431 Standard

16、Compliance Test of SFIA.2 TEST EQUIPMENTSFF-8431 Standard Compliance Test of SFIA.3 Host Transmitter Output Jitter and Eye Mask Specifications at B SFF-8431 Standard Compliance Test of SFI10GSFP+Cu DIRECT ATTACH CABLE Compliance Test 10GSFP+Cu cable assemblies are effectively constructed out of a pa

17、ir of SFP+ modules with the OE components replaced with copper cabling. The cable assembly shall incorporate DC blocking capacitors with at least 4.3 V rating on the RX side and with high pass pole of between 20 kHz and 100 kHz. The drain wire is connected to VeeT and to VeeR. The cable shield direc

18、tly connects the module A and B cases. B.1 10GSFP+Cu Direct Attach ConstructionSFF-8431 Standard Compliance Test of SFISFF-8431 Standard Compliance Test of SFIB.2 SFP+ Direct Attach Cable Test SetupSFF-8431 Standard Compliance Test of SFIB.3 10GSFP+Cu Cable Assembly Specifications at B and C Our Tes

19、t EnvironmentFigure 1Eye Diagram Test by DSA8200Key features of Test InstrumentsDSA8200 Digital Serial Analyzer DC to 65 GHz optical bandwidth; DC to 70+ GHz electrical bandwidth, with up to 12.5 GHz triggering. Bandwidth is determined by the capabilities of the installed modules;CR125A Electrical C

20、lock Recovery instrument100 Mb/s to 12.5 Gb/s continuous data rate coverage;Single-ended or differential 50 data inputs/outputs;DC coupled data through path;Insertion loss: -2.6dB when 12GHz80E04 Electrical Sample Module SMA RF coaxial cable with up to 18G bandwidth and the insertion loss is 1.4dB/m

21、 when 10GHz.Eye Diagram Test by DSA8200Installing Test EnvironmentCautionsDo NOT apply a signal outside the Maximum Input Voltage Swing; Always use a wrist strap when making signal connections;Discharge to ground any electrostatic charge that may be present on the center and outer conductors of cabl

22、es before attaching the cables to the instrument;Never install or remove modules while the instrument is powered on; Do NOT transport or ship the instrument with modules installed;If possible, always use ESD protection module(80E02) along the test path, example, TDR test ;Always disable the 80E04s T

23、DR function when not use the TDR function.Eye Diagram Test by DSA8200C.1 Acquainted with Our InstrumentDSA8200 Digital Serial AnalyzerEye Diagram Test by DSA8200Eye Diagram Test by DSA8200CR125A Electrical Clock Recovery instrumentEye Diagram Test by DSA820080E04 Electrical Sampling Module with TDR

24、function.Eye Diagram Test by DSA8200C.2 Eye Diagram Test Environment Setup of SFINotes：Please see the attached notes to set the eye diagram test setup.Step 1. Installing the hardware environment as “figure 1” showing;Eye Diagram Test by DSA8200Step 2. POWER ON the instruments and wait 20 minutes for

25、 instruments warm-up period ;Eye Diagram Test by DSA8200Step 3. Confirm the TDR function is DISABLED during the eye diagram test to avoid damage the 80E04 TDR module;Notes: Confirm those check-box under “TDR” SETUPS is unchecked to disable the TDR functions on the test channel.Eye Diagram Test by DS

26、A8200Step 4. Execute compensation and wait until the status of all items warm up to PASS ; If the status is Fail, rerun the compensation. If Fail status continues and you have allowed warm up to occur, the module or main instrument may need service.Step 5. Setting software environment;Setting the Di

27、splay StyleNotes: Select the Infinite Persistence on the “Disp” and the “fast sampling” mode on the front panel.Eye Diagram Test by DSA8200Setting triggerNotes: Select the External Prescaler as the trigger source.Eye Diagram Test by DSA8200Setting Math as sourcesEye Diagram Test by DSA8200Notes：For

28、differential signal eye test, subtract the two differential sources we using to define a math as the aimed signal source.Waveform DatabasesEye Diagram Test by DSA8200Notes：Select the math we had defined as the waveform database and choose the infinite mode to display it.Mask SettingEye Diagram Test

29、by DSA8200Notes：Select our aimed eye mask in the drop-down menu or import customer mask we had defined.Setting Measurements Eye Diagram Test by DSA8200Notes：Select the signal source and set signal type to “NRZ”. Then, set measurement we aimed to show on the screen, for example, eye height, eye width

30、, Pk-Pk jitter, RMS jitter, and so on.Set a STOP ActionEye Diagram Test by DSA8200Restart TestingEye Diagram Test by DSA8200Eye Diagram Test by DSA8200Step 3： Calibrate our test installingThe propagation delay inherent in connecting cables and probes can result in inaccurate amplitude and time-correlated measurements. To