電子信息工程測控技術(shù)與儀器外文翻譯外文文獻(xiàn)英文文獻(xiàn)

1、.PAGE ：.；PAGE 13外文出處：Springer-Link電子期刊附件1：外文資料翻譯譯文SJA1000 獨(dú)立的CAN控制器運(yùn)用指南1 引見SJA1000是一個(gè)獨(dú)立的CAN控制器，它在汽車和普通的工業(yè)運(yùn)用上有先進(jìn)的特征。由于它和PCA82C200 在硬件和軟件都兼容，因此它將會(huì)替代PCA82C200。SJA1000有一系列先進(jìn)的功能適宜于多種運(yùn)用，特別在系統(tǒng)優(yōu)化、診斷和維護(hù)方面非常重要。本文是要指點(diǎn)用戶設(shè)計(jì)基于SJA1000 的完好的CAN節(jié)點(diǎn)。同時(shí)本文還提供典型的運(yùn)用電路圖和編程的流程圖。2 概述SJA1000 獨(dú)立的CAN控制器有2個(gè)不同的操作方式：BasicCAN方式(和PCA

2、82C200兼容PeliCAN方式BasicCAN方式是上電后默許的操作方式。因此，用PCA82C200開發(fā)的已有硬件和軟件可以直接在SJA1000上運(yùn)用，而不用作任何修正。PeliCAN方式是新的操作方式，它可以處置一切CAN2.0B 規(guī)范的幀類型。而且它還提供一些加強(qiáng)功能使SJA1000能運(yùn)用于更寬的領(lǐng)域。2.1 CAN 節(jié)點(diǎn)構(gòu)造通常，每個(gè)CAN 模塊可以被分成不同的功能塊。SJA1000運(yùn)用3 4 5最優(yōu)化的CAN收發(fā)器銜接到CAN 。收發(fā)器控制從CAN控制器到總線物理層或相反的邏輯電平信號(hào)。上面一層是一個(gè)CAN 控制器，它執(zhí)行在CAN規(guī)范8里規(guī)定的完好的CAN協(xié)議。它通常用于報(bào)文緩沖和

3、驗(yàn)收濾波，而一切這些CAN功能，都由一個(gè)模塊控制器控制它擔(dān)任執(zhí)行運(yùn)用的功能。例如，控制執(zhí)行器、讀傳感器和處置人機(jī)接口MMI。如圖1所示，SJA1000獨(dú)立的CAN控制器通常位于微型控制器和收發(fā)器之間，大多數(shù)情況下這個(gè)控制器是一個(gè)集成電路。圖1 CAN模塊安裝2.2 構(gòu)造圖以下圖是SJA1000 的構(gòu)造圖圖2 SJA1000的構(gòu)造圖根據(jù)CAN規(guī)范，CAN中心模塊控制CAN幀的發(fā)送和接納。接口管理邏輯擔(dān)任銜接外部主控制器，該控制器可以是微型控制器或任何其他器件。經(jīng)過SJA1000復(fù)用的地址/數(shù)據(jù)總線訪問存放器和控制讀/寫選通訊號(hào)都在這里處置。另外，除了PCA82C200已有的BasicCAN功能，

4、還參與了一個(gè)新的PeliCAN 功能。因此，附加的存放器和邏輯電路主要在這塊里生效。SJA1000的發(fā)送緩沖器可以存儲(chǔ)一個(gè)完好的報(bào)文擴(kuò)展的或規(guī)范的。當(dāng)主控制器初始化發(fā)送，接口管理邏輯會(huì)使CAN 中心模塊從發(fā)送緩沖器讀CAN 報(bào)文。當(dāng)收到一個(gè)報(bào)文時(shí)，CAN中心模塊將串行位流轉(zhuǎn)換成用于驗(yàn)收濾波器的并行數(shù)據(jù)。經(jīng)過這個(gè)可編程的濾波器SJA1000 能確定主控制器要接納哪些報(bào)文。一切收到的報(bào)文由驗(yàn)收濾波器驗(yàn)收并存儲(chǔ)在接納FIFO。儲(chǔ)存報(bào)文的多少由任務(wù)方式?jīng)Q議，而最多能存儲(chǔ)32個(gè)報(bào)文。由于數(shù)據(jù)超載能夠性被大大降低，這運(yùn)用戶能更靈敏地指定中斷效力和中斷優(yōu)先級(jí)。3 系統(tǒng)為了銜接到主控制器，SJA1000提供一

5、個(gè)復(fù)用的地址/數(shù)據(jù)總線和附加的讀/寫控制信號(hào)。SJA1000可以作為主控制器外圍存儲(chǔ)器映射的I/O器件。3.1 SJA1000 的運(yùn)用SJA1000 的存放器和管腳配置使它可以運(yùn)用各種各樣集成或分立的CAN收發(fā)器。由于有不同的微控制器接口，運(yùn)用可以運(yùn)用不同的微控制器。圖3所示是一個(gè)包括80C51微型控制器和PCA82C251收發(fā)器的典型SJA1000運(yùn)用。CAN 控制器功能像是一個(gè)時(shí)鐘源，復(fù)位信號(hào)由外部復(fù)位電路產(chǎn)生。在這個(gè)例子里，SJA1000 的片選由微控制器的P2.7口控制。否那么，這個(gè)片選輸入必需接到VSS。它也可以經(jīng)過地址譯碼器控制，例如，當(dāng)?shù)刂?數(shù)據(jù)總線用于其他外圍器件的時(shí)侯。圖3

6、典型的SJA1000運(yùn)用3.2 電源SJA1000有三對(duì)電源引腳，用于CAN 控制器內(nèi)部不同的數(shù)字和模擬模塊。VDD1/VSS1：內(nèi)部邏輯 數(shù)字VDD2/VSS2：輸入比較器 模擬VDD3/VSS3： 輸出驅(qū)動(dòng)器 模擬為了有更好的EME性能，電源應(yīng)該分隔開來。例如為了抑制比較器的噪聲，VDD2 可以用一個(gè)RC濾波器來退耦。3.3 復(fù)位為了使SJA1000正確復(fù)位，CAN控制器的XTAL1管腳必需銜接一個(gè)穩(wěn)定的振蕩器時(shí)鐘見3.4節(jié)。引腳17的外部復(fù)位信號(hào)要同步并被內(nèi)部延伸到15個(gè)tXTAL。這保證了SJA1000 一切存放器可以正確復(fù)位見1 。要留意的是上電后的振蕩器的起振時(shí)間必需求思索。3.4

7、 振蕩器和時(shí)鐘戰(zhàn)略SJA1000能用片內(nèi)振蕩器或片外時(shí)鐘源任務(wù)。另外CLKOUT管腳可被使能，向主控制器輸出時(shí)鐘頻率。圖4顯示了SJA1000運(yùn)用的四個(gè)不同的定時(shí)原理。假設(shè)不需求CLKOUT信號(hào)，可以經(jīng)過置位時(shí)鐘分頻存放器Clock Off=1關(guān)斷。這將改善CAN節(jié)點(diǎn)的EME性能。CLKOUT信號(hào)的頻率可以經(jīng)過時(shí)鐘分頻存放器改動(dòng)：fCLKOUT = fXTAL / 時(shí)鐘分頻因子1，2，4，6，8 ，10 ，12 ，14。上電或硬件復(fù)位后，時(shí)鐘分頻因子的默許值由所選的接口方式引腳11決議。假設(shè)運(yùn)用16MHz的晶振，Intel 方式下CLKOUT 的頻率是8 MHz， Motorola 方式中復(fù)位

8、后的時(shí)鐘分頻因子是12，這種情況CLKOUT會(huì)產(chǎn)生1.33MHz的頻率。圖4 時(shí)鐘戰(zhàn)略3.4.1 睡眠和喚醒置位命令存放器的進(jìn)入睡眠位BasicCAN 方式或方式存放器PeliCAN方式的睡眠方式位后，假設(shè)沒有總線活動(dòng)和中斷等待，SJA1000就會(huì)進(jìn)入睡眠方式。振蕩器在15個(gè)CAN位時(shí)間內(nèi)堅(jiān)持運(yùn)轉(zhuǎn)形狀。此時(shí),微型控制器用CLKOUT頻率來計(jì)時(shí)，進(jìn)入本人的低功耗方式。假設(shè)出現(xiàn)三個(gè)喚醒條件之中的一個(gè)1，振蕩器會(huì)再次啟動(dòng)并產(chǎn)生一個(gè)喚醒中斷。振蕩器穩(wěn)定后，CLKOUT頻率被激活。3.5 CPU接口SJA1000支持直接銜接到兩個(gè)著名的微型控制器系列：80C51和68xx。經(jīng)過SJA1000的MODE引

9、腳可選擇接口方式： Intel方式： MODE 高M(jìn)otorola方式： MODE 低地址/數(shù)據(jù)總線和讀/寫控制信號(hào)在Intel方式和Motorola方式的銜接如圖5所示。Philips基于80C51系列的8位微控制器和XA構(gòu)造的16位微型控制器都運(yùn)用Intel 方式。為了和其他控制器的地址數(shù)據(jù)總線和控制信號(hào)匹配，必需求附加邏輯電路。但是必需確保在上電期間不產(chǎn)生寫脈沖。另一個(gè)方法在這個(gè)時(shí)候使片選輸入是高電平，禁能CAN 控制器。圖5 SJA1000的CPU時(shí)鐘接口3.6 物理層接口為了和PCA82C200兼容,SJA1000包括一個(gè)模擬接納輸入比較器電路。假設(shè)收發(fā)器的功能由分立元件實(shí)現(xiàn)，就要用

10、到這個(gè)集成的比較器。圖6 SJA1000的接納輸入比較器假設(shè)運(yùn)用外部集成收發(fā)器電路，而且沒有在時(shí)鐘分頻存放器里使能比較器旁路功能，RX1輸出要被銜接到2.5V 的參考電壓現(xiàn)有的收發(fā)器電路參考電壓輸出。圖6顯示了兩種設(shè)置的相應(yīng)電路：CBP=激活和CBP=非激活另外喚醒信號(hào)的通道被下拉對(duì)于運(yùn)用集成的收發(fā)器電路的一切新運(yùn)用我們建議激活運(yùn)用SJA1000的比較器旁路功能圖7。假設(shè)這個(gè)功能被使能，施密特觸發(fā)器的輸入有效，內(nèi)部的傳播延遲tD2比接納比較器的延遲tD1要小得多。它對(duì)最大的總線長度6有正面的影響。另外，休眠方式的電流將顯著降低。圖7 帶有集成收發(fā)器電路的規(guī)范運(yùn)用附件2：外文原文復(fù)印件SJA10

11、00 Stand-alone CAN controller1. INTRODUCTIONThe SJA1000 is a stand-alone CAN Controller product with advanced features for use in automotive and general industrial applications. It is intended to replace the PCA82C200 because it is hardware and software compatible. Due to an enhanced set of function

12、s this device is well suited for many applications especially when system optimization, diagnosis and maintenance are important.This report is intended to guide the user in designing complete CAN nodes based on the SJA1000. The report provides typical application circuit diagrams and flow charts for

13、 programming.2. OVERVIEWThe stand-alone CAN controller SJA1000 1has two different Modes of Operation:- BasicCAN Mode (PCA82C200 compatible)- PeliCAN ModeUpon Power-up the BasicCAN Mode is the default mode of operation. Consequently, existing hardware and software developed for the PCA82C200 can be u

14、sed without any change. In addition to the functions known from the PCA82C200 7, some extra features have been implemented in this mode which make the device more attractive. However, they do not influence the compatibility to the PCA82C200.The PeliCAN Mode is a new mode of operation which is able t

15、o handle all frame types according to CAN specification 2.0B 8. Furthermore it provides a couple of enhanced features which makes the SJA1000 suitable for a wide range of applications.2.1 CAN Node ArchitectureGenerally each CAN module can be divided into different functional blocks. The connection t

16、o the CAN bus lines is usually built with a CAN Transceiver optimized for the applications 3, 4, 5. The transceiver controls the logic level signals from the CAN controller into the physical levels on the bus and vice versa.The next upper level is a CAN Controller which implements the complete CAN p

17、rotocol defined in the CAN Specification 8. Often it also covers message buffering and acceptance filtering.All these CAN functions are controlled by a Module Controller which performs the functionality of the application. For example, it controls actuators, reads sensors and handles the man-machine

18、 interface (MMI).As shown in Figure 1 the SJA1000 stand-alone CAN controller is always located between a microcontroller and the transceiver, which is an integrated circuit in most cases. 2.2 Block DiagramThe following figure shows the block diagram of the SJA1000.The CAN Core Block controls the tra

19、nsmission and reception of CAN frames according to the CAN specification.The Interface Management Logic block performs a link to the external host controller which can be a microcontroller or any other device. Every register access via the SJA1000 multiplexed address/data bus and controlling of the

20、read/write strobes is handled in this unit. Additionally to the BasicCAN functions known from the PCA82C200, new PeliCAN features have been added. As a consequence of this, additional registers and logic have been implemented mainly in this block.The Transmit Buffer of the SJA1000 is able to store o

21、ne complete message (Extended or Standard). Whenever a transmission is initiated by the host controller the Interface Management Logic forces the CAN Core Block to read the CAN message from the Transmit Buffer.When receiving a message, the CAN Core Block converts the serial bit stream into parallel

22、data for the Acceptance Filter. With this programmable filter the SJA1000 decides which messages actually are received by the host controller.All received messages accepted by the acceptance filter are stored within a Receive FIFO. Depending on the mode of operation and the data length up to 32 mess

23、ages can be stored. This enables the user to be more flexible when specifying interrupt services and interrupt priorities for the system because the probability of data overrun conditions is reduced extremely. 3. SYSTEMFor connection to the host controller, the SJA1000 provides a multiplexed address

24、/data bus and additional read/write control signals. The SJA1000 could be seen as a peripheral memory mapped I/O device for the host controller.3.1 SJA1000 ApplicationConfiguration Registers and pins of the SJA1000 allow to use all kinds of integrated or discrete CAN transceivers. Due to the flexibl

25、e microcontroller interface applications with different microcontrollers are possible.In Figure 3 a typical SJA1000 application diagram including 80C51 microcontroller and PCA82C251 transceiver is shown. The CAN controller functions as a clock source and the reset signal is generated by an external

26、reset circuitry. In this example the chip select of the SJA1000 is controlled by the microcontroller port function P2.7. Instead of this, the chip select input could be tied to VSS. Control via an address decoder is possible, e.g., when the address/data bus is used for other peripherals.3.2 Power Su

27、pplyThe SJA1000 has three pairs of voltage supply pins which are used for different digital and analog internal blocks of the CAN controller.VDD1 / VSS1: internal logic (digital)VDD2 / VSS2: input comparator (analog)VDD3 / VSS3: output driver (analog)The supply has been separated for better EME beha

28、viour. For instance the VDD2 can be de-coupled via an RC3.3 ResetFor a proper reset of the SJA1000 a stable oscillator clock has to be provided at XTAL1 of the CAN controller, see also chapter 3.4. An external reset on pin 17 is synchronized and internally lengthened to 15 . This guarantees a correc

29、t reset of all SJA1000 registers (see 1). Note that an oscillator start-up time has to be taken into account upon power-up.3.4 Oscillator and Clocking StrategyThe SJA1000 can operate with the on-chip oscillator or with external clock sources. Additionally the CLK OUT pin can be enabled to output the

30、 clock frequency for the host controller. Figure 4 shows four different clocking principles for applications with the SJA1000. If the CLK OUT signal is not needed, it can be switched off with the Clock Divider register (Clock Off = 1). This will improve the EME performance of the CAN node.The freque

31、ncy of the CLK OUT signal can be changed with the Clock Divider Register:f CLK OUT = f XTAL / Clock Divider factor (1,2,4,6,8,10,12,14).Upon power up or hardware reset the default value for the Clock Divider factor depends on the selected interface mode (pin 11). If a 16 MHz crystal is used in Intel

32、 mode, the frequency at CLK OUT is 8 MHz. In Motorola mode a Clock Divider factor of 12 is used upon reset which results in 1,33 MHz in this case. 3.4.1 Sleep and Wake-upUpon setting the Go To Sleep bit in the Command Register (BasicCAN mode) or the Sleep Mode bit in the Mode Register (PeliCAN mode)

33、 the SJA1000 will enter Sleep Mode if there is no bus activity and no interrupt is pending. The oscillator keeps on running until 15 CAN bit times have been passed. This allows a microcontroller clocked with the CLK OUT frequency to enter its own low power consumption mode.If one of three possible w

34、ake-up conditions 1occurs the oscillator is started again and a Wake-up interrupt is generated. As soon as the oscillator is stable the CLK OUT frequency is active.3.5 CPU InterfaceThe SJA1000 supports the direct connection to two famous microcontroller families: 80C51 and 68xx. With the MODE pin of

35、 the SJA1000 the interface mode is selected.Intel Mode: MODE = highMotorola Mode: MODE = lowThe connection for the address/data bus and the read/write control signals in both Intel and Motorola mode is shown in Figure 5. For Philips 8-bit microcontrollers based on the 80C51 family and the 16-bit microcontrollers with XA architecture the Intel Mode is used.For other controllers additional glue logic is necessary for adaptation of the address/data bus and the control signals. However, it has to be made sure that no write pulses are generated during power-up. Another possibility is