數(shù)字系統(tǒng)設(shè)計(jì)與VHDL7-VHDL設(shè)計(jì)進(jìn)階

第7章

VHDL設(shè)計(jì)進(jìn)階7.1行為描述7.2數(shù)據(jù)流描述7.3結(jié)構(gòu)描述7.4三態(tài)邏輯設(shè)計(jì)7.5RAM存儲(chǔ)器設(shè)計(jì)7.6分頻器設(shè)計(jì)7.7數(shù)字跑表7.8音樂演奏電路主要內(nèi)容VHDL允許設(shè)計(jì)者用三種方式來對(duì)邏輯電路描述和建模

行為（Behavioural）描述；數(shù)據(jù)流（DataFlow）描述或寄存器傳輸級(jí)（RTL）描述；結(jié)構(gòu)（Structural）描述。所謂行為描述，就是對(duì)設(shè)計(jì)實(shí)體的數(shù)學(xué)模型的描述，其抽象程度遠(yuǎn)高于結(jié)構(gòu)描述方式。行為描述類似于高級(jí)編程語言，當(dāng)描述一個(gè)設(shè)計(jì)實(shí)體的行為時(shí)，無須知道具體電路的結(jié)構(gòu)，只需要描述清楚輸入與輸出信號(hào)的行為，而無須花費(fèi)精力關(guān)注設(shè)計(jì)結(jié)構(gòu)的具體實(shí)現(xiàn)。7.1

行為描述

【例7.1】行為描述方式實(shí)現(xiàn)的1位全加器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYfull_addaISPORT(a,b,cin:INSTD_LOGIC;

cout,sum:OUTSTD_LOGIC);ENDfull_adda;ARCHITECTUREbehavOFfull_addaISSIGNALtemp:STD_LOGIC_VECTOR(1DOWNTO0);BEGINtemp<=('0'&a)+b+cin;sum<=temp(0);

cout<=temp(1);ENDbehav;【例7.2】行為描述方式實(shí)現(xiàn)的2選1數(shù)據(jù)選擇器ENTITYmux21aISPORT(a,b,sel:INBIT;y:OUTBIT);ENDENTITYmux21a;ARCHITECTUREbehavOFmux21aISBEGIN

PROCESS(a,b,sel)BEGINIFsel='0'THENy<=a;ELSEy<=b;ENDIF;ENDPROCESS;ENDARCHITECTUREbehav;采用行為描述方式時(shí)應(yīng)注意下面幾點(diǎn)用行為描述方式設(shè)計(jì)電路，可以降低設(shè)計(jì)難度。行為描述只需表示輸入與輸出之間的關(guān)系，不需要包含任何結(jié)構(gòu)方面的信息。設(shè)計(jì)者只需寫出源程序，而電路的實(shí)現(xiàn)由EDA軟件自動(dòng)完成，實(shí)現(xiàn)電路的優(yōu)化程度，往往取決于綜合軟件的技術(shù)水平和器件的支持能力。在電路的規(guī)模較大或者需要描述復(fù)雜的邏輯關(guān)系時(shí)，應(yīng)首先考慮用行為描述方式進(jìn)行設(shè)計(jì)，如果設(shè)計(jì)的結(jié)果不能滿足資源占有率的要求，則應(yīng)改變描述方式。7.2

數(shù)據(jù)流描述【例7.4】數(shù)據(jù)流描述的1位全加器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYfull_addbISPORT(a,b,cin:INSTD_LOGIC;

sum,cout:OUTSTD_LOGIC);ENDfull_addb;ARCHITECTUREdataflowOFfull_addbISBEGINsum<=aXORbXORcin;

cout<=(aANDb)OR(bANDcin)OR(aANDcin);ENDdataflow;【例7.5】數(shù)據(jù)流描述的2選1數(shù)據(jù)選擇器ENTITYmux21cIS

PORT(a,b,sel:INBIT;y:OUTBIT);ENDENTITYmux21c;ARCHITECTUREdataflowOFmux21cISSIGNALa1,a2:BIT;BEGINa1<=aAND(NOTSel);a2<=bANDsel;y<=a1ORa2;ENDARCHITECTUREdataflow;7.3

結(jié)構(gòu)描述所謂結(jié)構(gòu)描述方式，就是指在設(shè)計(jì)中，通過調(diào)用庫中的元件或是已設(shè)計(jì)好的模塊來完成設(shè)計(jì)實(shí)體功能的描述。在結(jié)構(gòu)體中，描述只表示元件（或模塊）和元件（或模塊）之間的互連，就像網(wǎng)表一樣。當(dāng)調(diào)用庫中不存在的元件時(shí)，則必須首先進(jìn)行元件的創(chuàng)建，然后將其放在工作庫中，這樣才可以調(diào)用?！纠?.6】半加器的VHDL描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYhalf_addIS

PORT(a,b:INSTD_LOGIC;co,so:OUTSTD_LOGIC);ENDENTITYhalf_add;ARCHITECTUREoneOFhalf_addisBEGINso<=aXORb;co<=aANDb;ENDARCHITECTUREone;【例7.7】或門邏輯描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYor2hIS

PORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYor2h;ARCHITECTUREoneOFor2hISBEGINy<=aORb;ENDARCHITECTUREone;【例7.8】結(jié)構(gòu)描述的1位二進(jìn)制全加器頂層設(shè)計(jì)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYfull_addIS

PORT(ain,bin,cin:INSTD_LOGIC;

cout,sum:OUTSTD_LOGIC);ENDENTITYfull_add;ARCHITECTUREstructOFfull_addISCOMPONENThalf_add --將半加器定義為元件

PORT(a,b:INSTD_LOGIC;

co,so:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTor2h

PORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALd,e,f:STD_LOGIC; --定義3個(gè)信號(hào)作為內(nèi)部連線

BEGINu1:half_addPORTMAP(a=>ain,b=>bin,co=>d,so=>e);--元件例化

u2:half_addPORTMAP(a=>e,b=>cin,co=>f,so=>sum);u3:or2hPORTMAP(a=>d,b=>f,y=>cout);

ENDARCHITECTUREstruct;【例7.9】結(jié)構(gòu)描述的4位級(jí)聯(lián)加法器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYf_add4IS

PORT(a,b:INSTD_LOGIC_VECTOR(0TO3);

cin:INSTD_LOGIC;sum:OUTSTD_LOGIC_VECTOR(0TO3);

cout:OUTSTD_LOGIC);ENDENTITYf_add4;ARCHITECTUREstructOFf_add4ISCOMPONENTfull_add

--將1位全加器定義為元件

PORT(ain,bin,cin:INSTD_LOGIC;

cout,sum:OUTSTD_LOGIC);ENDCOMPONENT;

SIGNALci:STD_LOGIC_VECTOR(1TO3); --定義節(jié)點(diǎn)信號(hào)

BEGINu1:full_addPORTMAP(ain=>a(0),bin=>b(0),cin=>cin,

cout=>ci(1),sum=>sum(0)); --元件例化

u2:full_addPORTMAP(ain=>a(1),bin=>b(1),cin=>ci(1),

cout=>ci(2),sum=>sum(1));u3:full_addPORTMAP(ain=>a(2),bin=>b(2),cin=>ci(2),

cout=>ci(3),sum=>sum(2));u4:full_addPORTMAP(ain=>a(3),bin=>b(3),cin=>ci(3),cout=>cout,sum=>sum(3));ENDARCHITECTUREstruct;7.4三態(tài)邏輯設(shè)計(jì)

【例7.12】三態(tài)門LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtrigateISPORT(en,a:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDtrigate;ARCHITECTUREoneOFtrigateISBEGINy<=aWHEN(en='1')ELSE'Z';ENDone;【例7.13】三態(tài)雙向緩沖器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYbidirISPORT(y:INOUTSTD_LOGIC;--y為雙向I/O端口

en,a:INSTD_LOGIC;b:OUTSTD_LOGIC);ENDbidir;ARCHITECTUREoneOFbidirISBEGIN

y<=aWHEN(en='1')ELSE'Z';b<=y;ENDone;【例7.14】三態(tài)雙向緩沖器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYbidir1ISPORT(y:INOUTSTD_LOGIC;--y為雙向I/O端口

en,a:INSTD_LOGIC;b:OUTSTD_LOGIC);ENDbidir1;ARCHITECTUREoneOFbidir1ISBEGINPROCESS(en,a)BEGINIF(en='1')THENy<=a;ELSEy<='Z';ENDIF;ENDPROCESS;b<=y;ENDone;【例7.15】三態(tài)雙向總線緩沖器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYttl245ISPORT(a,b:INOUTSTD_LOGIC_VECTOR(7DOWNTO0); --雙向數(shù)據(jù)線

oe,dir:INSTD_LOGIC); --使能信號(hào)和方向控制ENDttl245;ARCHITECTUREoneOFttl245ISBEGINa<=bWHEN(oe='0'ANDdir='0')ELSE(OTHERS=>'Z');b<=aWHEN(oe='0'ANDdir='1')ELSE(OTHERS=>'Z');ENDone;三態(tài)雙向總線緩沖器RTL綜合視圖（SynplifyPro）

7.5RAM存儲(chǔ)器設(shè)計(jì)

生成一個(gè)新的宏模塊設(shè)置輸出文件的類型、目錄和名字定制RAM模塊的數(shù)據(jù)寬度和深度【例7.16】調(diào)用RAM宏模塊構(gòu)成RAM存儲(chǔ)器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;LIBRARYaltera_mf;USEaltera_mf.all;ENTITYram8x128IS --頂層模塊端口PORT(addr :INSTD_LOGIC_VECTOR(6DOWNTO0);

clk :INSTD_LOGIC; data :INSTD_LOGIC_VECTOR(7DOWNTO0);

aclr :INSTD_LOGIC;

wr :INSTD_LOGIC;

qout :OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDram8x128;ARCHITECTURElpmOFram8x128ISCOMPONENTramIS --將RAM模塊定義為元件

PORT(address:INSTD_LOGIC_VECTOR(6DOWNTO0); clock :INSTD_LOGIC; data :INSTD_LOGIC_VECTOR(7DOWNTO0);

aclr :INSTD_LOGIC; wren :INSTD_LOGIC; q :OUTSTD_LOGIC_VECTOR(7DOWNTO0) );ENDCOMPONENT;BEGINu1:ramPORTMAP(address=>addr,clock=>clk,data=>data,aclr=>aclr,wren=>wr,q=>qout); --元件例化ENDlpm;在實(shí)際中我們經(jīng)常會(huì)遇到這樣的問題，需要進(jìn)行奇數(shù)次分頻，同時(shí)又要得到占空比是50%的方波波形?？刹捎萌缦路椒ǎ河脙蓚€(gè)計(jì)數(shù)器，一個(gè)由輸入時(shí)鐘上升沿觸發(fā)，一個(gè)由輸入時(shí)鐘下降沿觸發(fā)，最后將兩個(gè)計(jì)數(shù)器的輸出相或，即可得到占空比為50%的方波波形。

7.6分頻器設(shè)計(jì)7.6.1占空比為50%的奇數(shù)分頻

【例7.18】占空比50%的奇數(shù)分頻（模7）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYfdiv7IS

PORT(clk,reset:INSTD_LOGIC;

clkout:OUTSTD_LOGIC); --輸出時(shí)鐘ENDfdiv7;ARCHITECTUREbehavOFfdiv7ISSIGNALclkout1,clkout2:STD_LOGIC;SIGNALcount1,count2:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(clk) --計(jì)數(shù)器1BEGIN

IF(clk'eventANDclk='1')THEN --上升沿觸發(fā)

IF(reset='1')THENcount1<="0000";ELSEIF(count1=6)THENcount1<="0000";ELSEcount1<=count1+1;ENDIF;IF(count1<3)THENclkout1<='1';ELSEclkout1<='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(clk) --計(jì)數(shù)器2BEGIN

IF(clk'eventANDclk='0')THEN --下降沿觸發(fā)

IF(reset='1')THENcount2<="0000";ELSEIF(count2=6)THENcount2<="0000";ELSEcount2<=count2+1;ENDIF;IF(count2<3)THENclkout2<='1';ELSEclkout2<='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;clkout<=clkout1ORclkout2; --相或ENDbehav;模7奇數(shù)分頻器功能仿真波形圖（QuartusⅡ）

【例7.19】較為通用的占空比為50%的奇數(shù)分頻電路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYfdivnISGENERIC(w:INTEGER:=11); --定義類屬參量w

PORT(clk,reset:INSTD_LOGIC;

clkout:OUTSTD_LOGIC); --輸出時(shí)鐘ENDfdivn;ARCHITECTUREbehavOFfdivnISSIGNALclkout1,clkout2:STD_LOGIC;SIGNALcount1,count2:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(clk) --計(jì)數(shù)器1BEGIN

IF(clk'eventANDclk='1')THEN --上升沿觸發(fā)

IF(reset='1')THENcount1<="0000";ELSEIF(count1=w-1)THENcount1<="0000";ELSEcount1<=count1+1;ENDIF;IF(count1<(w-1)/2)THENclkout1<='1';ELSEclkout1<='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(clk) --計(jì)數(shù)器2BEGIN

IF(clk'eventANDclk='0')THEN --下降沿觸發(fā)

IF(reset='1')THENcount2<="0000";ELSEIF(count2=w-1)THENcount2<="0000";ELSEcount2<=count2+1;ENDIF;IF(count2<(w-1)/2)THENclkout2<='1';ELSEclkout2<='0';ENDIF;ENDIF;ENDIF;NDPROCESS;clkout<=clkout1ORclkout2; --相或ENDbehav;模11奇數(shù)分頻器功能仿真波形圖（QuartusⅡ）

【例7.20】n0.5半整數(shù)分頻器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYfdivn_5IS

PORT(clkin,clr:INSTD_LOGIC;

clkout:BUFFERSTD_LOGIC); --輸出時(shí)鐘ENDfdivn_5;ARCHITECTUREoneOFfdivn_5ISconstantn:std_logic_vector(3downto0):="0100"; --分頻預(yù)置數(shù)nSIGNALclk2,clk1:STD_LOGIC;SIGNALcount:STD_LOGIC_VECTOR(3DOWNTO0);BEGINclk2<=clkinXORclk1; --clkin與clk1異或后作為模N計(jì)數(shù)器的時(shí)鐘PROCESS(clk2,clr)BEGIN

IF(clr='1')THENcount<="0000";7.6.2半整數(shù)分頻

ELSIF(clk2'eventANDclk2='1')THEN

IF(count=n-1)THEN --模n計(jì)數(shù)

count<="0000";

clkout<='1';ELSEcount<=count+1;

clkout<='0';ENDIF;ENDIF;ENDPROC