數(shù)電qutaras-典型電路的設計案例

典型電路設計案例1、計數(shù)器設計LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcountISGeneric(n:integer:=3);PORT(clk:inSTD_LOGIC;q:outSTD_LOGIC_vector(n-1downto0));ENDcount;ARCHITECTUREaOFcountISsignaltmp:STD_LOGIC_vector(n-1downto0);BEGINprocess(clk)beginifclk'eventandclk='1'thentmp<=tmp+1;endif;endprocess;q<=tmp;ENDa;an位二進制加法計數(shù)器24進制計數(shù)器ENQAQBCLKLIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount24ISPORT(en,Reset,clk:inSTD_LOGIC;

qa:outSTD_LOGIC_VECTOR(3DOWNTO0);--個位數(shù)計數(shù)

qb:outSTD_LOGIC_VECTOR(1DOWNTO0));--十位數(shù)計數(shù)ENDcount24;ARCHITECTUREa1OFcount24ISBEGINprocess(clk)variabletma:STD_LOGIC_VECTOR(3DOWNTO0);variabletmb:STD_LOGIC_VECTOR(1DOWNTO0);ResetbeginIfReset=‘0‘thentma:="0000";tmb:="00";else

ifclk'eventandclk='1'thenifen='1'theniftma="1001"thentma:="0000";tmb:=tmb+1;--如果個位數(shù)為9，個位數(shù)清零，十位數(shù)加一

elsif

tmb="10"andtma="0011"then

tma:="0000";tmb:="00";--如果十位數(shù)為2，個位數(shù)為3，個位數(shù)十位數(shù)均清零

elsetma:=tma+1;--以上條件均不滿足，則個位數(shù)加一

endif;

endif;endif;endif;qa<=tma;qb<=tmb;將結果輸出endprocess;ENDa1;LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount60ISPORT(en,Reset,clk:inSTD_LOGIC;

qa:outSTD_LOGIC_VECTOR(3DOWNTO0);--個位數(shù)計數(shù)

qb:outSTD_LOGIC_VECTOR(2DOWNTO0);--十位數(shù)計數(shù)

rco:OUTSTD_LOGIC);--計數(shù)進位ENDcount60;ARCHITECTUREaOFcount60ISBEGINprocess(clk)variabletma:STD_LOGIC_VECTOR(3DOWNTO0);variabletmb:STD_LOGIC_VECTOR(2DOWNTO0);60進制計數(shù)器ENQAQBCLKRCOResetbeginIfReset=‘0’thentma:="0000";

tmb:="0000";elseifclk'eventandclk='1'thenifen='1'thenrco<=tmb(2)andtmb(0)andtma(3)andtma(0);--計算是否有進位，即是否計數(shù)超過59，超過則有進位，否則無進位

iftma="1001"thentma:="0000";--如果個位數(shù)為9，則個位數(shù)清零

iftmb="101"thentmb:="000";elsetmb:=tmb+1;endif;

--如果十位數(shù)為5，則十位數(shù)清零，否則十位數(shù)加一

elsetma:=tma+1;--如果個位數(shù)不為9，則個位數(shù)加一

endif;endif;

endif;endif;qa<=tma;qb<=tmb;將結果輸出endprocess;ENDa;2、分頻器設計

計數(shù)器就是對時鐘脈沖計數(shù)，同時計數(shù)器還是一個分頻器。下圖為一個3位的計數(shù)器的仿真波形圖。<1>一個3bits的計數(shù)器，它所能計數(shù)的范圍為0~7（=23-1）。同理，nbits的計數(shù)器所能計數(shù)范圍為0~2n-1。<2>Q0、Q1、Q2的波形頻率分別為時鐘脈沖信號Clk的1/2、1/4、1/8，由此可以知道，nbits的計數(shù)器可獲得的最低分頻頻率為時鐘脈沖信號Clk的1/2n。<3>輸出信號Q(2downto0)的頻率等于信號Q2的頻率，信號Q(2downto1)的頻率也為信號Q2的頻率。由此可以知道，矢量信號的頻率為最高位信號的頻率。<4>對于4MHz頻率信號，若得到1Hz時鐘脈沖信號Clk，通過公式f=1/2n可計算出n≈22，即應設計一個22位的計數(shù)器。4MHz到1Hz的分頻器

LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcountISPORT(clk:inSTD_LOGIC;q:outSTD_LOGIC;ENDcount;ARCHITECTUREaOFcountISsignaltmp:STD_LOGIC_vector(21downto0);Beginprocess(clk)beginifclk'eventandclk='1'thentmp<=tmp+1;endif;endprocess;q<=tmp(21);ENDa;十進制計數(shù)器

LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount10ISPORT(clk:INSTD_LOGIC;

seg:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDcount10;ARCHITECTUREa1OFcount10ISsignalsec:STD_LOGIC;signalq:STD_LOGIC_VECTOR(21DOWNTO0);signalnum:STD_LOGIC_VECTOR(3DOWNTO0);BEGINprocess(clk)----get1hzclockpulsebeginifclk'eventandclk='1'thenq<=q+1;endif;sec<=q(21);--get1hzclockpulseendprocess;timing:process(sec)beginifsec'eventandsec='1'thenifnum<9thennum<=num+1;elsenum<="0000";endif;endif;endprocess;B1:block--bcd-7segsBegin--gfedcbaseg<="0111111"whennum=0else"0000110"whennum=1else"1011011"whennum=2else"1001111"whennum=3else"1100110"whennum=4else"1101101"whennum=5else"1111101"whennum=6else"0000111"whennum=7else"1111111"whennum=8else"1101111"whennum=9else"0000000";endblock;ENDa1;3交通燈控制器的設計

設計一個十字路口交通燈控制器，東西、南北方向有紅燈、黃燈、綠燈，持續(xù)時間分別為45、5、40秒。東西方向b南北方向a十字路口東西方向b南北方向a十字路口交通燈控制器ClkRaYaGaYbRbGb電路框圖GA,RBT=40S?NoYesYA,RBT=5S?NoYesRA,GBT=40S?NoYesRA,YBT=5S?NoYes交通燈控制流程圖S0S1S2S3LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYnclightISPort(clk:instd_logic;

ra,rb,ya,yb,ga,gb:outstd_logic);ENDnclight;Architectureaofnclightistypestateis(S0,S1,S2,S3);signalpresentstate,nextstate:state;signaltmp1,tmp2:integerrange0to40;signaltimeout1,timeout2:std_logic;signalq:std_logic_vector(21downto0);signalsec:std_logic;Begin----get1hzclockpulseprocess(clk)beginifclk'eventandclk='1'thenq<=q+1;endif;sec<=q(21);--get1hzclockpulseendprocess;timing:process(sec)beginifsec'eventandsec='1'then

iftmp1=39thentimeout1<='1';timeout2<='0';tmp1<=0;elseiftimeout1='1'then

iftmp2=4thentimeout2<='1';timeout1<='0';tmp2<=0;elsetmp2<=tmp2+1;endif;

elsetmp1<=tmp1+1;endif;endif;

endif;endprocess;changestate:process(presentstate)Begincasepresentstateis

whenS0=>iftimeout1='0'then

nextstate<=s0;

ra<='0';

ya<='0';ga<='1';

rb<='1';

yb<='0';gb<='0';elsenextstate<=s1;endif;whenS1=>iftimeout2='0'then

nextstate<=s1;

ra<='0';ya<='1';

ga<='0';

rb<='1';yb<='0';gb<='0';elsenextstate<=s2;endif;whenS2=>iftimeout1='0'then

nextstate<=s2;

ra<='1';

ya<='0';ga<=‘1';

rb<='0';yb<='0';gb<='1';

elsenextstate<=s3;endif;whenS3=>iftimeout2='0'then

nextstate<=s3;

ra<='1';

ya<='0';ga<='0';

rb<='0';yb<='1';

gb<='0';elsenextstate<=s0;endif;

whenothers=>nextstate<=s0;timeout1<='0';timeout2<='0';

endcase;endprocess;enda;4、數(shù)控分頻器設計

對于一個加法計數(shù)器，裝載不同的計數(shù)初始值時，會有不同頻率的溢出輸出信號。計數(shù)器溢出時，輸出‘1’電平，同時溢出時的‘1’電平反饋給計數(shù)器的輸入端作為裝載信號；否則輸出‘0’電平。Libraryieee;Useieee.std_logic_1164.all;EntityspeakerisPort(

clk:instd_logic;

Freq_num:inintegerrange0to2047；--16#7FF#speaker:outstd_logic);Endspeaker;Architecturea1ofspeakerissignalpower_speaker:std_logic;beginProcess(clk)variablecount11bit:integerrange0to2047;Beginifclk'eventandclk='1'thenifcount11bit=2047thencount11bit:=Freq_num;

power_speaker<='1';Elsecount11bit:=count11bit+1;

power_speaker<='0';endif;endif;endprocess;--將輸出再進行2分頻，將脈沖展寬，以使揚聲器有足夠功率發(fā)音process(power_speaker)variablecount2bit:std_logic;Beginifpower_speaker'eventandpower_speaker='1'then

count2bit:=notcount2bit;ifcount2bit='1'thenspeaker<='1';elsespeaker<='0';endif;endif;endprocess;Enda1;C調音階頻率表

音階頻率/Hz音階頻率/Hz音階頻率/Hz1661.227830.61415.311479.986739.99370.001318.525659.33329.631174.664587.33293.671108.733554.37277.19987.762493.88246.94880.001440.00220.00參考代碼表clk=1MHz計數(shù)器的模為2048

音調音符1234567初始值高1730175017701790181518301930中1410149015601600162216501690低77391210361116119712901372次低100200300400500600700音樂演奏電路

35

635—65

312—設計框圖數(shù)控分頻器揚聲器驅動電路揚聲器Freq_numClk1MHz分頻器4Hz16進制計數(shù)器ROM模塊SpeakerIndexLibraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitytoneisPort(index:inintegerrange0to16;tone:outintegerrange0to16#7FF#);Endtone;Architecturea1oftoneisBeginprocess(index)Begin35

635—65

312—caseindexiswhen0=>

tone<=1560;when1=>

tone<=1622;when2=>

tone<=1650;when3=>

tone<=1560;when4=>

tone<=1622;when5=>

tone<=1622;when6=>

tone<=1622;when7=>

tone<=1622;

when8=>

tone<=1650;when9=>

tone<=1622;when10=>tone<=1560;when11=>tone<=1410;when12=>tone<=1490;when13=>tone<=1490;when14=>tone<=1490;when15=>tone<=1490;

whenothers=>tone<=2047;Endcase;Endprocess;Enda1;35

635—65

312—音調音符1234567初始值高1730175017701790181518301930中1410149015601600162216501690低77391210361116119712901372次低100200300400500600700Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitytopisPort(clk:instd_logic;spkout:outstd_logic);Endtop;Architecturea1oftopiscomponenttonePort(index:inintegerrange0to16;tone:outintegerrange0to16#7FF#);endcomponent;componentspeakerPort(clk:instd_logic;

Freq_in:inintegerrange0to16#7FF#;speaker:outstd_logic);endcomponent;signalindex1:integerrange0to16;signaltone2:integerrange0to16#7FF#;signalck4:std_logic;beginprocess(clk)variableq:std_logic_vector(17downto0);Beginifclk'eventandclk='1'thenq:=q+1;

endif;ck<=q(17);endprocess;process(ck)Beginifck'eventandck='1'thenifindex1=15thenindex1<=0;elseindex1<=index1+1;

endif;endif;endprocess;u1:toneportmap(index1,tone2);u2:speakerportmap(clk,tone2,spkout);Enda1;例2：用lpm_rom兆函數(shù)模塊實現(xiàn)七段碼顯示0-F。

IP核的使用（提高電路設計效率的有效方法）

LPM宏單元庫分為：

門單元函數(shù)，如：lpm_and，lpm_mux…

算術運算函數(shù)，如：lpm_add_sub，

lpm_mult

存貯函數(shù)，如：lpm_ff，lpm_rom…

七段顯示譯碼電路七段碼顯示:abcdefg1.七段譯碼關系表如下：

a[3..0] a,b,c,d,e,f,g 0 1,1,1,1,1,1,