設(shè)計(jì)參考、源碼手冊1746個(gè)avce6467t數(shù)字媒體片上系統(tǒng)

VCE6467T,AVCE6467TVCE6467T,查詢樣品VCE6467T

ZHCS058–MARCH–1-GHz+8000C64xMIPS/

數(shù)據(jù)信號處理器(DSP)擴(kuò)展指令和單一周期ARM?Jazelle?點(diǎn)到點(diǎn)SIP呼 –高達(dá)720p30分辨率和幀速單32位,雙16位,或者四倍8位 –低延遲和A/V同步兩個(gè)倍乘器支持四個(gè)16x16位乘法(32位 –帶寬管理控果)每時(shí)鐘周期或者八個(gè)8x8位乘法(16位 –包括基本封裝[只對AVCE6467T適用果)每時(shí)鐘周 –前向糾錯(FEC)[只對AVCE6467T適用 –音頻 附加的C64x+?增 H.264 H.264SVC(可擴(kuò) 編碼)[ ?具有4KB內(nèi)存的內(nèi)嵌緩沖區(qū)(ETB11?)，用 ?字節(jié)序：用于ARM和DSP的小字節(jié) ?雙重可編 位域提取,設(shè)定,清 –支持廣泛的編碼、和轉(zhuǎn)碼操 H.264,MPEG2,VC1,MPEG4 ?108-MHz接口 –兩個(gè)8位SD(BT.656),單個(gè)16位HD –兩個(gè)8位SD(BT.656)或者單個(gè)16位 設(shè)定 ?數(shù)據(jù)轉(zhuǎn)換引擎 –水平和垂直縮 –色度轉(zhuǎn)換S ?兩個(gè)傳輸流接口(TSIF)模塊支持32位和16位（Thumb模式）指令 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddierstheretoappearsattheendofthisdatasheet.?2011,TexasInstrumentsAlltrademarksarethe?2011,TexasInstrumentsPRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofall EnglishDataSheet: –支持高達(dá)1.8432Mbps –SIR和MIR(0.576M波特率 –具有可編程數(shù)據(jù)編碼的 ?具有兩個(gè)選擇的一個(gè)串行外設(shè)接口(SPI) ?主/從內(nèi)置集成電路(I2CBus?)外部器接口 ?兩個(gè)多通道音頻串行接口 –一個(gè)四串行器發(fā)送/接受端 –用于S/PDIF的一個(gè)單一DIT發(fā)送接 ?32位主機(jī)端口接節(jié)地 ?VLYNQ?接口(FPGA接口閃存接 ?兩個(gè)脈沖寬度調(diào)節(jié)器 )輸 ?ATA/ATAPII/F(ATA/ATAPI-6標(biāo)準(zhǔn) ?高達(dá)33個(gè)通用I/O(GPIO)陣腳(與其它設(shè)備功能多 器存取 復(fù)用控制器(64個(gè)獨(dú)立通道 ?片上ARMROM引導(dǎo)加載程序 ?為ARM/DSP的單獨(dú)省電模10/100/1000Mb/s以太網(wǎng)MAC ?靈活時(shí)鐘發(fā)生IEEE802.3兼容(只對3.3-VI/O適用 ?IEEE-1149.1 管理數(shù)據(jù)I/O(MDIO)模 ?529針無鉛型BGA封 (ZUT后綴),0.8-mm焊接間USB2.0高-/全-速客戶 ?0.09-μm/7-級Cu金屬處理器USB2.0高-/全-/低-速主 ?3.3-V和1.8-VI/O,1.3-V內(nèi)(迷你主機(jī),支持一個(gè)外 ?應(yīng)用設(shè)備 編碼 32位,66-MHz,3.3 組件互聯(lián)(PCI)主/從接 –數(shù)符合PCI標(biāo)準(zhǔn) –網(wǎng)絡(luò)媒介編碼 時(shí)器 –電視會VCE6467TAVCE6467TTMS320DM646x?DMSoC平臺的一部分TI’sDaVinci技術(shù)滿足下一代在這整篇文檔中除非特別注明VCE6467TVCE6467TAVCE6467TVCE6467T使得OEMs和ODMs能快速上市并具有穩(wěn)健操作系統(tǒng)支持的特性同時(shí)具有豐富的用戶界面高處理性能,更長的電池，這一切都是憑借全集成化混合處理器解決方案所具有的極大靈活性。一個(gè)共同處理器15CP15在TMS320C6000DSP平臺中，TMS320C64xDSPs是最高性能的定點(diǎn)DSPTI開發(fā)的增強(qiáng)型二代高性能，先進(jìn)的超長指令集結(jié)構(gòu)，這使得這些DSP成為數(shù)字媒介應(yīng)用的杰出選擇。C64x是C6000DSPTMS320C64x+DSP是C64xDSP的增強(qiáng)型組件，它具有C64xDSPC64xCPU的任何參考材料除非特別注明同樣分別適用于C64xDSPC64xCPU因?yàn)樵谝粋€(gè)1GHz時(shí)鐘頻率下的性能高達(dá)80億條指令,C64x+提供高性能DSP編程任務(wù)解決方案。DSP具有高速控制器的運(yùn)行靈活性和陣列處理器的數(shù)字能力。C64x+DSP處理器具有64個(gè)32位字長的通用寄存器和8—兩個(gè)運(yùn)算結(jié)果為32位的倍乘器和6(ALUs)8個(gè)功能單元包括在和成像應(yīng)用中起到加速作用的指令。DSP每個(gè)時(shí)鐘周期能夠生成四個(gè)16-位累積乘法(MACs)，每秒鐘總數(shù)為40億MACs(MMACS),或者每時(shí)鐘周期8個(gè)8位MACs，總數(shù)達(dá)到8000MMACS的每時(shí)鐘周期8個(gè)8位MACs。要獲得C64x+DSP的細(xì)節(jié),請查看TMS320C64x/C64x+DSPCPU和指令集參考手冊(文獻(xiàn)號SPRU732).VCE6467T也具有特定應(yīng)用的硬件邏輯晶載內(nèi)存和附加的晶載外設(shè)，這一點(diǎn)與其他C6000DSP平臺設(shè)備速緩存，而Level1數(shù)據(jù)高速緩存(L1D)則為640k位的組相關(guān)聯(lián)高速緩存。Level2程序高速緩存外設(shè)包括：一個(gè)可設(shè)置的端口;一個(gè)具有管理數(shù)據(jù)輸入/輸出(MDIO)模塊的10/100/1000Mb/s以太網(wǎng)MAC(EMAC一個(gè)4位傳輸/4VLYNQ接口一個(gè)內(nèi)部集成電路總線接口具有4個(gè)串行器的一個(gè)多通(McASP0具有一個(gè)單一發(fā)送串行器的一個(gè)備用多通道音頻串行接口(McASP12個(gè)64位通用計(jì)時(shí)器，每個(gè)可設(shè)置成2個(gè)獨(dú)立的32位計(jì)時(shí)器;1個(gè)64位計(jì)時(shí)器;一個(gè)可設(shè)置的32位主機(jī)端口接口(HPI);具有可編程中斷/生成模式的高達(dá)33針的通用輸入/輸出(GPIO),與其它 個(gè)UART/IrDA/CIR接口，在UART0上具有調(diào)制解調(diào)器接口信號;2個(gè)脈沖寬度調(diào)節(jié)器( )外設(shè);一個(gè)ATA/ATAPI-6接口;一個(gè)66-MHz外設(shè)組件接口(PCI);和2個(gè)外部器接口:一個(gè)異步外部 (EMIFA)以滿足慢速器/外設(shè),和用于DD2的一個(gè)高速同步內(nèi)存接口。持10Base-T和100Base-TX或者10M位/(Mbps)和100Mbps在半雙工或者全雙工和1000Base-TX(1管理數(shù)據(jù)輸入/(MDIO模塊持續(xù)輪詢32個(gè)MDIO地址以計(jì)算系統(tǒng)內(nèi)所有的PHYARM選擇出模塊并能可選擇的中斷ARM,允許ARM在不連續(xù)執(zhí)行高代價(jià)的MDIO而輪詢到設(shè)備的連接狀態(tài)。PCIHPII2CSPIUSB2.0VLYNQVCE6467T很容易的控制外設(shè)設(shè)備并/或與主機(jī)處理器通VCE6467T也包括一個(gè)/成像共同處理器(HDVICP)數(shù)據(jù)轉(zhuǎn)換引擎(VDCE)以減輕DSP的很多和成像的處理任務(wù),以使得DSPMIPS可從事普通和成像的算法。請與離您最近的TI銷售代表聯(lián)系以獲得HDVICP增強(qiáng)編碼，例如H.264和MPEG4，的信息。VCE6467T擁有一套用于ARM和DSPC語言編譯器、用于簡化程序設(shè)計(jì)和調(diào)度的DSP匯編優(yōu)化器以及旨在將可視性引入源代碼執(zhí)行的Windows?調(diào)試程序界面。JTAGJTAGSystemARMDSPARM926EJ-SC64x?DSP16I-8128KBL232KB32 32L1 L18KBProgram/Data1-1VCE6467TZHCS058–MARCH數(shù) 片上系統(tǒng)(DMSoC) Parameter

mendedClockandControlSignalTransition Power 功能方框圖 ExternalClockInputFromDeviceOverview andAUX_MXI/AUX_CLKIN Device Device ARM DSP

Clock EnhancedDirectMemoryAccess VCESoftwareAPIs ExternalMemoryInterface MemoryMapSummary 6.10DDR2Memory PinAssignments PortInterface TerminalFunctions 6.12TransportStreamInterface DeviceSupport 6.13ClockRecoveryGenerator ationSupport DataConversionEngine Community Device SystemModule Power Clock Boot ConfigurationsAt

PeripheralComponentInterconnect EthernetMAC ManagementDataInput/Output Host-PortInterface(HPI) USB2.0[see ATA MultichannelAudioSerialPortConfigurationsAfterReset MultiplexedPinConfigurations 6.23SerialPeripheralInterface DebuggingConsiderations 6.24UniversalAsynchronouseSystem DeviceOperating AbsoluteumRatingsOverOperating

.25Inter-IntegratedCircuit 6.26PulseWidthModulator( General-PurposeInput/Output mendedGeneral-PurposeInput/Output mendedOperatingConditionsIEEE1149.1 ElectricalCharacteristics MechanicalPackagingandTemperature(UnlessOtherwise RangesofSupplyVoltageTemperature(UnlessOtherwise PeripheralInformationand

ThermalDatafor Specifications Packaging DeviceDeviceTable2-1providesanoverviewoftheVCE6467TSoC.Thetableshowssignificantfeaturesofthedevice,includingthecapacityofon-chipRAM,peripherals,internalperipheralbusfrequencyrelativetotheC64x+DSP,andthepackagetypewithpincount.Table2-1.CharacteristicsoftheVCE6467TNotallperipheralspinsareavailableatthesametime(formoredetail,seetheDeviceConfigurationsDDR2MemoryDDR2(Upto400-MHz,16/32-bitbusAsynchronousEMIFAsynchronous(8/16-bitbuswidth)RAM,Flash(NOR,NAND)64independent8QDMA264-BitGeneralPurpose(eachconfigurableas2separate32-bittimers)164-Bit3(withSIR,MIR,CIRsupportandRTS/CTSflow(UART0SupportsModem1(supports2slave1MultichannelAudioSerialPort2(onetransmit/receivewith4serializers,oneDITtransmitonlywith1serializerforS/PDIF10/100/1000EthernetMACwithManagementDataInput/Output(MDIO)1(withMII/GMII1General-PurposeInput/OutputPortUpto3321(ATA/ATAPI-1(32-bit,661(16-/32-bitmultiplexed1[horizontalandverticaldownscaling,chromaconversion(4:2:2?4:2:0)]ClockRecoveryGenerator1PowerSleepController1(peripheral/moduleclock108-MHzConfigurablePortInterface28-bitBT.656capturechannels116-bitY/Ccapturechannel capturechannel8-bitBT.656 ychannels116-bitY/C yTransportStreamInterfaceMPEGtransportstream1with8-bitparallelorserialinputandoutput1withserial-onlyinputandoutputEachwithcorrespondingclockrecoverygenerator(CRGEN)forexternalVCXOcontrol.USB2.0High-andFull-SpeedDeviceHigh-,Full-,andLow-SpeedHostUSB2.0isnotsupportedon-1GpartsthataredatedpriortoMay1,2010.SeetheTMS320DM6467TSiliconErrata(LitureNumber:SPRZ307)formoredetailsonhowtodecodethedatefrompackagemarkings.Table2-1.CharacteristicsoftheVCE6467TProcessor(On-ChipSize248KBRAM,8KB32KBL1Program(L1P)/Cache(upto32KBL1Data(L1D)/Cache(upto128KBUnifiedMappedRAM/Cache16KBI-8KBD-32KB8KBCPUID+CPURevControlStatusRegister(addresslocation:0x01812000)JTAGJTAGID(addresslocation:0x01C4SeeSection6.29.1,JTAGID(JTAGID)RegisterCPUDSP1GHz(-ARM926500MHz(-CycleDSP1.0ns(-ARM9262.0ns(-Core1.3V(-I/O1.8V,3.3V(-PLL(Between27–35-MHzrange)x1(Bypass),x14tox32(-(Between27–35-MHzrange)x1(Bypass),x14tox32(-24/48-MHzBGA19x19529-PinBGAProcess0.09ProductProductPreview(PP),orProductionData(PD)PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.DeviceTheARM926EJ-SRISCCPUiscompatiblewithotherARM9CPUsfromARMHoldingsTheC64x+DSPcoreis patiblewiththeC6000?DSPtformandsupportsfeaturesoftheC64xTDSPfamily.ARMTheARMSubsystemisdesignedtogivetheARM926EJ-S(ARM9)mastercontrolofthedevice.Ingeneral,theARMisresponsibleforconfigurationandcontrolofthedevice;includingtheDSPSubsystem,theVPSSSubsystem,andamajorityoftheperipheralsandexternalmemories.TheARMSubsystemincludesthefollowingARM926EJ-SRISCARMv5TEJ(32/16-bit)instructionLittleendianCo-Processor1516KBInstruction8KBDataWrite32KBInternalTightly-CoupledMemory(TCM)RAM(32-bitwide8KBInternalROM(ARMbootloaderfornon-EMIFAbootEmbeddedTraceModuleandEmbeddedTraceBufferARMInterruptPLLPowerandSleepControllerSystemARM926EJ-SRISCTheARMSubsystemintegratestheARM926EJ-Sprocessor.TheARM926EJ-SprocessorisamemberofARM9familyofgeneral-purposemicroprocessors.Thisprocessoristargetedatmulti-taskingapplicationswherefullmemorymanagement,highperformance,lowdiesize,andlowpowerareallimportant.TheARM926EJ-Sprocessorsupportsthe32-bitARMand16bitTHUMBinstructionsets,enablingtheusertotradeoffbetweenhighperformanceandhighcodedensity.Specifically,theARM926EJ-SprocessorsupportstheARMv5TEJinstructionset,whichincludesfeaturesforefficientexecutionofJavabytecodes,providingJavaperformancesimilartoJustinTime(JIT)Javainterpreter,butwithoutassociatedcodeTheARM926EJ-SprocessorsupportstheARMdebugarchitectureandincludeslogictoassistinbothhardwareandsoftwaredebug.TheARM926EJ-SprocessorhasaHarvardarchitectureandprovidesacompletehighperformancesubsystem,including:ARM926EJ-SintegerCP15systemcontrolMemoryManagementUnitSeparateinstructionanddataWriteSeparateinstructionanddataTightly-CoupledMemories(TCMs)[internalRAM]SeparateinstructionanddataAHBbusEmbeddedTraceModuleandEmbeddedTraceBufferFormorecompletedetailsontheARM9,refertotheARM926EJ-STechnicalReferenceManual,availableTheARM926EJ-Ssystemcontrolcoprocessor(CP15)isusedtoconfigureandcontrolinstructionanddatacaches,Tightly-CoupledMemories(TCMs),MemoryManagementUnit(MMU),andotherARMsubsystemfunctions.TheCP15registersareprogrammedusingtheMRCandMCRARMinstructions,whentheARMinaprivilegedmodesuchassupervisororsystemmode.TheARM926EJ-SMMUprovidesvirtualmemoryfeaturesrequiredbyoperatingsystemssuchasLinux?,Windows?CE,Ultron?,ThreadX?,etc.Asinglesetoftwolevelpagetablesstoredinmainmemoryisusedtocontroltheaddresstranslation,permissionchecksandmemoryregionattributesforbothdataandinstructionaccesses.TheMMUusesasingleunifiedTranslationLookasideBuffer(TLB)tocachetheinformationheldinthepagetables.TheMMUfeaturesare:StandardARMarchitecturev4andv5MMUmap sandaccessprotectionMapsizes1MB64KB(large4KB(small1KB(tinyAccesspermissionsforlargepagesandsmallpagescanbespecifiedsepara yforeachquarterofthepage(subpagepermissions)HardwarepagetableInvalidateentireTLB,usingCP15registerInvalidateTLBentry,selectedbyMVA,usingCP15registerLockdownofTLBentries,usingCP15registerCachesandWriteThesizeoftheInstructionCacheis16KB,Datacacheis8KB.Additionally,theCacheshavethefollowingVirtualindex,virtualtag,andaddressedusingtheModifiedVirtualAddressFour-waysetassociative,withacachelinelengthofeightwordsperline(32-bytesperline)andwithtwodirtybitsintheDcacheDcachesupportswrite-throughandwrite-back(orcopyback)cacheoperation,selectedbymemoryregionusingtheCandBbitsintheMMUtranslationtables.Critical-wordfirstcacheCachelockdownregistersenablecontroloverwhichcachewaysareusedforallocationonalinefill,providingamechanismforbothlockdown,andcontrollingcachecorruptionDcachestoresthePhysicalAddressTAG(PATAG)correspondingtoeachDcacheentryintheTAGRAMforuseduringthecachelinewrite-backs,inadditiontotheVirtualAddressTAGstoredintheTAGRAM.ThismeansthattheMMUisnotinvolvedinDcachewrite-backoperations,removingthepossibilityofTLBmissesrelatedtothewrite-backaddress.Cachemaintenanceoperationsprovideefficientinvalidationof,theentireDcacheorIcache,regionsoftheDcacheorIcache,andregionsofvirtualmemory.Thewritebufferisusedforallwritestoanoncachablebufferableregion,write-throughregionandwritemissestoawrite-backregion.AseparatebufferisincorporatedintheDcacheforholdingwrite-backforcachelineevictionsorcleaningofdirtycachelines.Themainwritebufferhas16-worddatabufferandafour-addressbuffer.TheDcachewrite-backhaseightdatawordentriesandasingleaddressentry.TightlyCoupledMemoryARMinternalRAMisprovidedforstoringreal-timeandperformance-criticalcode/dataandtheInterruptVectortable.ARMinternalROMenablesnon-EMIFAbootoptions,suchasNANDandUART.TheRAMandROMmemoriesinterfacedtotheARM926EJ-Sviathetightlycoupledmemoryinterfacethatprovidesforseparateinstructionanddatabusconnections.SincetheARMTCMdoesnotallowinstructionsontheD-TCMbusordataontheI-TCMbus,anarbiterisincludedsothatbothdataandinstructionscanbestoredintheinternalRAM/ROM.ThearbiteralsoallowsaccessestotheRAM/ROMfromextra-ARMsources(e.g.,EDMAorothermasters).TheARM926EJ-Shasbuilt-inDMAsupportfordirectaccessestotheARMinternalmemoryfromanon-ARMmaster.Becauseofthetime-criticalnatureoftheTCMlinktotheARMinternalmemory,allaccessesfromnon-ARMdevicesaretreatedasDMAtransfers.InstructionandDataaccessesaredifferentiatedviaaccessingdifferentmemorymapregions,withtheinstructionregionfrom0x0000through0x7FFFanddatafrom0x10000through0x17FFF.Theinstructionregionat0x0000anddataregionat0x10000maptothesamephysical32-KBTCMRAM.cingtheinstructionregionat0x0000isnecessarytoallowtheARMInterruptVectortabletobecedat0x0000,asrequiredbytheARMarchitecture.Theinternal32-KBRAMissplitintotwophysicalbanksof16KBeach,whichallowssimultaneousinstructionanddataaccessestobe plishedifthecodeanddataareinseparatebanks.AdvancedHigh-PerformanceBusTheARMSubsystemusestheAHBportoftheARM926EJ-StoconnecttheARMtotheConfigbusandtheexternalmemories.ArbitersareemployedtoarbitrateaccesstotheseparateD-AHBandI-AHBbytheConfigBusandtheexternalmemoriesbus.EmbeddedTraceMacrocell(ETM)andEmbeddedTraceBufferTosupportreal-timetrace,theARM926EJ-SprocessorprovidesaninterfacetoenableconnectionofanEmbeddedTraceMacrocell(ETM).TheARM926ES-JSubsystemintheVCE6467TalsoincludestheEmbeddedTraceBuffer(ETB).TheETMconsistsoftwoparts:TracePortprovidesreal-timetracecapabilityfortheTriggeringfacilitiesprovidetriggerresources,whichincludeaddressanddatacomparators,counter,andTheVCE6467TtraceportisnotpinnedoutandisinsteadonlyconnectedtotheEmbeddedTraceBuffer.TheETBhasa4KBbuffermemory.ETBenableddebugtoolsarerequiredtoread/interpretthecapturedtracedata.ARMMemoryTheARMmemorymapisshowninSection2.6,MemoryMapSummaryofthis .TheARMhasaccesstomemoriesshowninthefollowingsections.ARMInternalTheARMhasaccesstothefollowingARMinternal32KBARMInternalRAMonTCMinterface,logicallyseparatedintotwo16KBpagestoallowsimultaneousaccessonanygivencycleifthereareseparateaccessesforcode(I-TCMbus)anddata(D-TCM)tothedifferentmemoryregions.8KBARMInternalExternalTheARMhasaccesstothefollowingexternalDDR2SynchronousAsynchronousEMIF/NORFlash/NANDDSPTheARMhasaccesstothefollowingDSPL2L1PL1DARM-DSPVCE6467TARMandDSPintegrationfeaturesareasDSPvisibilityfromARM’smemorymap,seeSection2.6,MemoryMapSummary,forBootModesforDSP-seeDeviceConfigurationssection,Section3.4.1,DSPBoot,forARMcontrolofDSPboot/reset-seeDeviceConfigurationssection,Section,ARMBoot,forARMcontrolofDSPisolationandpowerdown/powerup-seeSection3,DeviceConfigurations,forARM&DSPInterrupts-seeSection6.8.1,ARMCPUInterrupts,andSection6.8.2,DSPInterrupts,forTheARM9hasaccesstoalloftheperipheralsontheVCE6467TPLLControllerTheARMSubsystemincludesthePLLController.ThePLLControllercontainsasetofregistersforconfiguringVCE6467T’stwointernalPLLs(PLL1andPLL2).ThePLLControllerprovidesthefollowingconfigurationandcontrol:PLLBypassSetPLLmultiplierSetPLLdividerPLLpowerOscillatorpowerThePLLsarebrieflydescribedinthis intheClockingsection.FormoredetailedinformationonthePLLsandPLLControllerregisterdescriptions,seetheTMS320DM646xDMSoCARMSubsystemReferenceGuide(liturenumberSPRUEP9).PowerandSleepControllerTheARMSubsystemincludesthePowerandSleepController(PSC).ThroughregistersettingsaccessiblebytheARM9,thePSCprovidestwolevelsofpowersavings:peripheral/moduleclockgatingand shut-off.BriefdetailsonthePSCaregiveninSection6.3,Powers.FormoredetailedinformationandcompleteregisterdescriptionsforthePSC,seetheTMS320DM646xDMSoCARMSubsystemReferenceGuide(liturenumberSPRUEP9).ARMInterruptControllerTheARMInterruptController(AINTC)acceptsdeviceinterruptsandmapsthemtoeithertheARM’sIRQ(interruptrequest)orFIQ(fastinterruptrequest).TheARMInterruptControllerisbrieflydescribedinthisintheInterruptssection.FordetailedinformationontheARMInterruptController,seetheTMS320DM646xDMSoCARMSubsystemReferenceGuide(liturenumberSystemTheARMSubsystemincludestheSystemmodule.TheSystemmoduleconsistsofasetofregistersforconfiguringandcontrollingavarietyofsystemfunctions.FordetailsandregisterdescriptionsfortheSystemmodule,seeSection3,DeviceConfigurationsandseetheTMS320DM646xDMSoCARMSubsystemReferenceGuide(liturenumberSPRUEP9).PowerVCE6467Thasseveralmeansofmanagingpowerconsumption.Thereisextensiveuseofclockgating,whichreducesthepowerusedbyglobaldeviceclocksandindividualperipheralclocks.Clockmanagementcanbeutilizedtoreduceclockfrequenciesinordertoreduceswitchingpower.Formoredetailsonpowermanagementtechniques,seeSection3,DeviceConfigurations,Section6,PeripheralandElectricalSpecifications,andseetheTMS320DM646xDMSoCARMSubsystemReferenceGuide(liturenumberVCE6467Tgivestheprogrammerfullflexibilitytouseanyandallofthepreviouslymentionedcapabilitiestocustomizeanoptimalpowermanagementstrategy.Severaltypicalpowermanagementscenariosaredescribedinthefollowingsections.DSPTheDSPSubsystemincludesthefollowingC64x+DSP32KBL1Program(L1P)/Cache(upto32KBL1Data(L1D)/Cache(upto128KBUnifiedMappedRAM/CacheLittleC64x+DSPCPUTheC64x+CentralProcessingUnit(CPU)consistsofeightfunctionalunits,tworegisterfiles,andtwodatapathsasshowninFigure2-1.Thetwogeneral-purposeregisterfiles(AandB)eachcontain3232-bitregistersforatotalof64registers.Thegeneral-purposeregisterscanbeusedfordataorcanbedataaddresspointers.Thedatatypessupportedincludepacked8-bitdata,packed16-bitdata,32-bitdata,40-bitdata,and64-bitdata.Valueslargerthan32bits,suchas40-bit-longor64-bit-longvaluesarestoredinregisterpairs,withthe32LSBsofdatacedinanevenregisterandtheremaining8or32MSBsinthenextupperregister(whichisalwaysanodd-numberedregister).Theeightfunctionalunits(.M1,.L1,.D1,.S1,.M2,.L2,.D2,and.S2)areeachcapableofexecutingoneinstructioneveryclockcycle.The.Mfunctionalunitsperformallmultiplyoperations.The.Sand.Lunitsperformageneralsetofarithmetic,logical,andbranchfunctions.The.Dunitsprimarilyloaddatafrommemorytotheregisterfileandstoreresultsfromtheregisterfileintomemory.TheC64x+CPUextendstheperformanceoftheC64xcorethroughenhancementsandnewEachC64x+.Munitcanperformoneofthefollowingeachclockcycle:one32x32bitmultiply,one16x32bitmultiply,two16x16bitmultiplies,two16x32bitmultiplies,two16x16bitmultiplieswithadd/subtractcapabilities,four8x8bitmultiplies,four8x8bitmultiplieswithaddoperations,andfour16x16multiplieswithadd/subtractcapabilities(includingacomplexmultiply).ThereisalsosupportforGaloisfieldmultiplicationfor8-bitand32-bitdata.ManycommunicationsalgorithmssuchasFFTsandmodemsrequirecomplexmultiplication.Thecomplexmultiply(CMPY)instructiontakesfor16-bitinputsandproducesa32-bitrealanda32-bitimaginaryoutput.Therearealsocomplexmultiplieswithroundingcapabilitythatproducesone32-bitpackedoutputthatcontain16-bitrealand16-bitimaginaryvalues.The32x32bitmultiplyinstructionsprovidetheextendedprecisionnecessaryforaudioandotherhigh-precisionalgorithmsonavarietyofsignedandunsigned32-bitdatatypes.The.Lor(ArithmeticLogicUnit)nowincorporatestheabilitytodoparalleladd/subtractoperationsonapairofcommoninputs.Versionsofthisinstructionexisttoworkon32-bitdataoronpairsof16-bitdataperformingdual16-bitaddandsubtractsinparallel.Therearealsosaturatedformsoftheseinstructions.TheC64x+coreenhancesthe.Sunitinseveralways.IntheC64xcore,dual16-bitMIN2andMAX2comparisonswereonlyavailableonthe.Lunits.OntheC64x+coretheyarealsoavailableonthe.Sunitwhichincreasestheperformanceofalgorithmsthatdosearchingandsorting.Finally,toincreasedatapackingandunpackingthroughput,the.Sunitallowssustainedhighperformanceforthequad8-bit/16-bitanddual16-bitinstructions.Unpackinstructionsprepare8-bitdataforparallel16-bitoperations.Packinstructionsreturnparallelresultstooutputprecisionincludingsaturationsupport.OthernewfeaturesSPLOOP-AsmallinstructionbufferintheCPUthataidsincreationofsoftwarepipeliningloopswheremultipleitionsofaloopareexecutedinparallel.TheSPLOOPbufferreducesthecodesizeassociatedwithsoftwarepipelining.Furthermore,loopsintheSPLOOPbufferarefullyinterruptible.CompactInstructions-ThenativeinstructionsizefortheC6000devicesis32bits.ManycommoninstructionssuchasMPY,AND,OR,ADD,andSUBcanbeexpressedas16bitsiftheC64x+compilercanrestrictthecodetousecertainregistersintheregisterfile.Thiscompressionisperformedbythecodegenerationtools.InstructionSetEnhancement-Asnotedabove,therearenewinstructionssuchas32-bitmultiplications,complexmultiplications,packing,sorting,bitmanipulation,and32-bitGaloisfieldmultiplication.ExceptionsHandling-Intendedtoaidtheprogrammerinisolatingbugs.TheC64x+CPUisabletodetectandrespondtoexceptions,bothfrominternallydetectedsources(suchasillegalop-codes)andfromsystemevents(suchasawatchdogtimeexpiration).Privilege-Definesuserandsupervisormodesofoperation,allowingtheoperatingsystemtogiveabasiclevelofprotectiontosensitiveresources.Localmemoryisdividedintomultiplepages,eachwithread,write,andexecutepermissions.Time-StampCounter-PrimarilytargetedforReal-TimeOperatingSystem(RTOS)robustness,-runningtime-stampcounterisimplementedintheCPUwhichisnotsensitivetosystemFormoredetailsontheC64x+CPUanditsenhancementsovertheC64xarchitecture,seethefollowingTMS320C64x/C64x+DSPCPUandInstructionSetReferenceGuide turenumberTMS320C64xTechnicalOverview turenumberfilefileA(A1,323283232fileB(B0,3232fileB(B1,32328Controllongsrceven.L2odd8.S2oddlong longevendstodd 8oddlongfileA(A0,DatapathDatapathOn.Munit,dst2is32On.Munit,dst1is32OnC64xCPU.Munit,src2is32bits;onC64x+CPU.Munit,src2is64Figure2-1.TMS320C64x+?CPU(DSPCore)DataDSPMemoryTheDSPmemorymapisshowninSection2.6,MemoryMapSummary.ConfigurationofthecontrolregistersforDDR2,EMIFA,andARMInternalRAMissupportedbytheARM.TheDSPhasaccesstomemoriesshowninthefollowingsections.ARMInternalTheDSPhasaccesstothe32KBARMInternalRAMontheARMD-TCMinterface(i.e.,dataExternalTheDSPhasaccesstothefollowingExternalDDR2SynchronousAsynchronousEMIF/NORDSPInternalTheDSPhasaccesstothefollowingDSPL2L1PL1DC64x+TheC64x+coreusesatwo-levelcache-basedarchitecture.TheLevel1Programmemory/cache(L1P)consistsof32KBmemoryspacethatcanbeconfiguredasmappedmemoryordirectmappedcache.TheLevel1Datamemory/cache(L1D)consistsof32KBthatcanbeconfiguredasmappedmemoryor2-waysetassociatedcache.TheLevel2memory/cache(L2)consistsofa128KBRAMmemoryspacethatissharedbetweenprogramanddataspace.L2memorycanbeconfiguredasmappedmemory,cache,oracombinationofboth.Table2-2showsamemorymapoftheC64x+CPUcacheregistersfortheTable2-2.C64x+CacheHEXADDRESSREGISTER0x0184L2Cacheconfiguration0x0184L1PSizeCacheconfiguration0x0184 zeModeCacheconfiguration0x0184L1DSizeCacheconfiguration0x0184L1DzeModeCacheconfiguration0x01840048-0x0184-0x0184L2EDMAaccesscontrol0x01841004-0x0184-0x0184L2allocationregister0x0184L2allocationregister0x0184L2allocationregister0x0184L2allocationregister0x01842010-0x0184-0x0184L2writebackbaseaddress0x0184L2writebackwordcount0x0184L2writebackinvalidatebaseaddress0x0184L2writebackinvalidatewordcount0x0184L2invalidatebaseaddressTable2-2.C64x+CacheRegisters HEXADDRESSREGISTER0x0184L2invalidatewordcount0x0184L1Pinvalidatebaseaddress0x0184L1Pinvalidatewordcount0x0184L1Dwritebackinvalidatebaseaddress0x0184L1Dwritebackinvalidatewordcount0x0184-0x0184L1DBlock0x0184L1DBlock0x0184L1Dinvalidatebaseaddress0x0184L1Dinvalidatewordcount0x01844050-0x0184-0x0184L2writebackall0x0184L2writebackinvalidateall0x0184L2GlobalInvalidatewithout0x0184500C-0x0184-0x0184L1PGlobal0x0184502C-0x0184-0x0184L1DGlobal0x0184L1DGlobalWritebackwith0x0184L1DGlobalInvalidatewithout0x01848000-0x0184MAR0-(correspondstobyteaddress0x00000000-0x0FFFFFFF)0x0184MemoryAttributeRegistersforARMTCM(correspondstobyteaddress0x10000000-0x10FFFFFF)0x01848044-0x0184MAR17-(correspondstobyteaddress0x11000000-0x3FFFFFFF)0x0184(correspondstobyteaddress0x40000000-0x40FFFFFF)0x0184(correspondstobyteaddress0x41000000-0x41FFFFFF)0x01848108-0x0184MAR66-MemoryAttributeRegistersforEMIFA(correspondstobyteaddress0x42000000-0x49FFFFFF)0x01848128-0x0184MAR74-(correspondstobyteaddress0x4A000000-0x4BFFFFFF)0x01848130-0x0184MAR76-MemoryAttributeRegistersforVLYNQ(correspondstobyteaddress0x4C000000-0x4FFFFFFF)0x01848140-0x0184MAR80-(correspondstobyteaddress0x50000000-0x7FFFFFFF)0x01848200-0x0184MAR128-MemoryAttributeRegistersforDDR2(correspondstobyteaddress0x80000000-0xBFFFFFFF)0x01848300-0x0184MAR192-(correspondstobyteaddress0xC0000000-0xFFFFFFFF)TheDSPhasaccess/controllabilityofthefollowing2Timers(Timer0andTimer1)thatcaneachbeconfiguredas164-bitor232-bitDSPInterruptTheDSPInterruptControlleracceptsdeviceinterruptsandappropriaymapsthemtotheDSP’savailableinterrupts.TheDSPInterruptControllerisbrieflydescribedinthis intheInterruptssection.FormoredetailedontheDSPInterruptController,seetheTMS320C64x+DSPMegamoduleReferenceGuide(liturenumberSPRU871).VCESoftwareFigure2-2showsthesoftwareblockdiagramoftheCallSignalingCommontformandOperatingMediaFigure2-2.SoftwareBlockTheTexasInstruments(TI)VCE6467TtakesadvantageoftheRADVISION?softwareinfrastructu