信號(hào)與系統(tǒng)第

1Chapter8SequentialLogicDesignPractices

(時(shí)序邏輯設(shè)計(jì)實(shí)踐)SSILatchesandFlip-Flops(SSI型鎖存器和觸發(fā)器)MSIDevice:Counters,ShiftRegisters(MSI器件：計(jì)數(shù)器、移位寄存器)Others:Documents,Iterative,FailureandMetastability(其它：文檔、迭代、故障和亞穩(wěn)定性)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)28.1Sequential-CircuitDocumentationStandards(時(shí)序電路文檔標(biāo)準(zhǔn))8.1.1GeneralRequirements

(一般要求)8.1.2LogicSymbols(邏輯符號(hào))：Edge-Triggered,Master/SlaveOutput

(邊沿觸發(fā)、主從輸出)AsynchronousPreset(attheTop)andClear(attheBottom)(異步預(yù)置（頂端）、異步清零（底端）)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)38.1Sequential-CircuitDocumentationStandards(時(shí)序電路文檔標(biāo)準(zhǔn))8.1.3State-MachineDescription(狀態(tài)機(jī)描述)Worddescriptions,Statetables,StateDiagrams,TransitionLists

(文字、狀態(tài)表、狀態(tài)圖、狀態(tài)轉(zhuǎn)移列表)8.1.4TimingDiagramsandSpecifications

(時(shí)序圖及其規(guī)范)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)4CLOCK觸發(fā)器輸出組合電路輸出觸發(fā)器輸入建立時(shí)間容限保持時(shí)間容限即：組合電路輸出（觸發(fā)器激勵(lì)）必須在觸發(fā)器輸入要求的建立時(shí)間之前到達(dá)。5CLOCK觸發(fā)器輸出組合電路輸出觸發(fā)器輸入建立時(shí)間容限保持時(shí)間容限即：組合電路下一次的輸出必須在觸發(fā)器輸入要求的保持時(shí)間之后到達(dá)。68.2LatchesandFlip-Flops

(鎖存器和觸發(fā)器)8.2.1SSILatchesandFlip-Flops1Q1Q2Q2Q3Q3Q4Q4Q1,2C1D2D3,4C3D4D74x375D

LatchesPRDQCLKQCLR74x74PRJQCLKK

QCLR74x109PRJQCLKK

QCLR74x112Figure8-3引腳DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)78.2.2SwitchDebouncing(開關(guān)消抖)+5VSW_LDSWPush(開關(guān)閉合)SW_LDSWPush(開關(guān)閉合)FirstContact(閉合第1次接觸)ContactBounce(觸點(diǎn)抖動(dòng))SW_LDSWIdealCase(理想情況)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)8SW_LSW0011SW_LSW0011Push(開關(guān)閉合)0011SW_LSW0011SW_LSW1100DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)單刀雙擲(SPDT,Single-pole,Double-throw)優(yōu)點(diǎn):1、使用芯片數(shù)少;2、不需要上拉電阻;3、可以產(chǎn)生兩種極性的輸入信號(hào).9SW_LSWDSWPush(開關(guān)閉合)Figure8-5問題：為什么不應(yīng)該同高速CMOS器件一起使用？QQLSQRQ+5VDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)避免門輸出發(fā)生瞬時(shí)短路108.2.4BusHolderCircuit

(總線保持電路)三態(tài)總線：任何時(shí)刻，最多只有一個(gè)輸出可以驅(qū)動(dòng)總線DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)沒有輸出去驅(qū)動(dòng)總線，總線“懸空”，會(huì)如何？造成流入器件輸出端的電流過大解決辦法：接上拉電阻到高電平問題：上拉電阻阻值的選??？過大，RC時(shí)間常數(shù)大，轉(zhuǎn)換時(shí)間慢過小，消耗的電流太多118.2.4BusHolderCircuit

(總線保持電路)ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSRC0SRC1SRC2P0P1P7SDATADigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)線路由高/低變?yōu)閼铱諘r(shí)，總線保持原態(tài)線路在高/低間轉(zhuǎn)換時(shí)，總線通過電阻R提供小電流12DQCQDQCQDQCQDQCQDIN[3:0]WRDOUT[3:0]RD8.2.5MultibitRegistersandLatches

(多位鎖存器和寄存器)回顧：鎖存器的應(yīng)用——多位鎖存器寄存器（register）共用同一時(shí)鐘的多個(gè)D觸發(fā)器組合在一起通常用來存儲(chǔ)一組相關(guān)的二進(jìn)制數(shù)。134-bitRegister

(4位寄存器74x175)6位寄存器74x174Figure8-91D2D3D4DCLKCLR_LDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)148-bitRegister74x374（三態(tài)輸出）Figure8-10OE輸出使能1574x377（時(shí)鐘使能）74x273（異步清零）CLK74x374（輸出使能）1674x377（ClockEnable,時(shí)鐘使能）ENEN’二選一多路復(fù)用結(jié)構(gòu)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)17寄存器（register）和鎖存器（latch）有什么區(qū)別？寄存器：邊沿觸發(fā)特性鎖存器：C有效期間輸出跟隨輸入變化74x374輸出使能8位寄存器74x373輸出使能8位鎖存器DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)188.4Counter(計(jì)數(shù)器)Modulus:Thenumberofstatesinthecycle（模：循環(huán)中的狀態(tài)個(gè)數(shù)）Amodulo-mcounter,orsometimes,adivide-by-mcounter

(模m計(jì)數(shù)器,又稱m分頻計(jì)數(shù)器）AnyclocksequentialcircuitwhosestatediagramContainaSinglecycle.(狀態(tài)圖中包含有一個(gè)循環(huán)的任何時(shí)鐘時(shí)序電路)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)198.4Counter(計(jì)數(shù)器)Ann-bitbinarycounter(n位二進(jìn)制計(jì)數(shù)器)S1S2S3SmS5S4ENENENENENENENEN’EN’EN’EN’EN’EN’DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)20計(jì)數(shù)器的分類按時(shí)鐘：同步、異步按計(jì)數(shù)方式：加法、減法、可逆按編碼方式：二進(jìn)制、十進(jìn)制BCD碼、循環(huán)碼計(jì)數(shù)器的功能計(jì)數(shù)、分頻、定時(shí)、產(chǎn)生脈沖序列、數(shù)字運(yùn)算本節(jié)內(nèi)容行波計(jì)數(shù)器、同步計(jì)數(shù)器MSI型計(jì)數(shù)器及其應(yīng)用二進(jìn)制計(jì)數(shù)器狀態(tài)的譯碼DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)218.4.1RippleCounters（行波計(jì)數(shù)器）

利用T觸發(fā)器實(shí)現(xiàn)：Q*=Q’QQT考慮二進(jìn)制計(jì)數(shù)順序：只有當(dāng)?shù)趇-1位由10時(shí)，第i位才翻轉(zhuǎn)。CLKQQTQQTQQTQQTQ0Q1Q2Q3DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)00-01-10-11-00CLKQQTQQTQQTQQTQ0Q1Q2Q3CLKQ0Q1Q2速度慢，最壞情況，第n位在時(shí)鐘觸發(fā)后延遲n×tTQ才出現(xiàn)Q34×tTQ異步時(shí)序23SynchronousBinaryUpCounters

(同步二進(jìn)制加法計(jì)數(shù)器)1011011+11011100在多位二進(jìn)制數(shù)的末位加1，僅當(dāng)?shù)趇位以下的各位都為1時(shí)，第i位的狀態(tài)才會(huì)改變。最低位的狀態(tài)每次加1都要改變。EN

QTQ

利用有使能端的T觸發(fā)器實(shí)現(xiàn)：Q*=EN·Q’+EN’·Q=ENQ通過EN端進(jìn)行控制，需要翻轉(zhuǎn)時(shí)，使EN=1ENi=Qi-1·Qi-2·…·Q1·Q0EN0=?1DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)248.4.2SynchronousCounter

(同步計(jì)數(shù)器)1CLKQ0Q1Q2C如何加入使能端？DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)低位LSB高位MSB25SynchronousCounterswithEnableInput

(有使能端的同步計(jì)數(shù)器)CNTEN低位LSB高位MSB串行使能DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)26CNTEN并行使能高位MSB低位LSBDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)SynchronousCounterswithEnableInput

(有使能端的同步計(jì)數(shù)器)27SynchronousBinaryUpCounters

(同步二進(jìn)制加法計(jì)數(shù)器)1011011+11011100在多位二進(jìn)制數(shù)的末位加1，僅當(dāng)?shù)趇位以下的各位都為1時(shí)，第i位的狀態(tài)才會(huì)改變。最低位的狀態(tài)每次加1都要改變。對(duì)于D觸發(fā)器：Q*=DDi=(Qi-1·…·Q1·Q0)QDQCLKQ=ENQ考慮T觸發(fā)器：Q*=ENQ

利用D觸發(fā)器實(shí)現(xiàn)：D0=1Q=Q’DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)28MSICounters(MSI計(jì)數(shù)器)74x161、74x1634-BitBinaryUp-Counters(withAsynchronous/SynchronousClear)(4位二進(jìn)制加法計(jì)數(shù)器（異、同步清零）)74x160、74x1621-BitDecade(BCDCode)Up-Counters(withAsynchronous/SynchronousClear)(1位十進(jìn)制（BCD）加法計(jì)數(shù)器（異、同步清零）)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)29MSICounter(MSI計(jì)數(shù)器)74x1694-BitBinaryUp/DownCounter(4位二進(jìn)制可逆計(jì)數(shù)器)計(jì)數(shù)器可以用作分頻器DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)8.4.3MSIcountersandapplications

(MSI型計(jì)數(shù)器及應(yīng)用)同步4位二進(jìn)制計(jì)數(shù)器74x163——模16計(jì)數(shù)器同步清零同步預(yù)置數(shù)進(jìn)位輸出使能端74x163的功能表01111CLK工作狀態(tài)同步清零同步置數(shù)保持保持,RCO=0計(jì)數(shù)CLR_LLD_LENPENT0111

00

1174x161是異步清零RCO異步清零清零時(shí),QA=QB=QC=QD=0

置數(shù)時(shí),QA=A,QB=B,QC=C,QD=DDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)74x163的

邏輯電路圖采用D觸發(fā)器

便于實(shí)現(xiàn)清零

和加載預(yù)置數(shù)Figure8-2811111在計(jì)數(shù)值達(dá)到最大時(shí)，立即進(jìn)位74x163的同步清零功能LD_LCLR_LAQA01000000同或門計(jì)數(shù)功能的電路Qi*=(Qi-1·…·Q1·Q0)Qi=(Qi-1·…·Q1·Q0)⊙

QNi

DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)74x163的同步預(yù)置數(shù)功能LD_LCLR_LAQA0010A0A1A同或門計(jì)數(shù)功能的電路Qi*=(Qi-1·…·Q1·Q0)Qi=(Qi-1·…·Q1·Q0)⊙

QNi

DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)74x163的自由運(yùn)行模式自行循環(huán)計(jì)數(shù)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)74x163的自由運(yùn)行模式自由運(yùn)行的74x163可以用作2、4、8和16分頻計(jì)數(shù)器36OtherMSICounters(其它MSI計(jì)數(shù)器)74x160、74x1621位十進(jìn)制（BCD）加法計(jì)數(shù)器（異、同步清零）01234567890QAQBQCQDQC、QD都是十分頻，但占空比不是50％DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)3774x169可逆計(jì)數(shù)器74x160、74x1621位十進(jìn)制（BCD）加法計(jì)數(shù)器（異、同步清零）UP/DNUP/DN=1加法計(jì)數(shù)（升序）UP/DN=0減法計(jì)數(shù)（降序）使能輸入進(jìn)位輸出低電平有效DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)OtherMSICounters(其它MSI計(jì)數(shù)器)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)8.4.4二進(jìn)制計(jì)數(shù)器狀態(tài)的譯碼398.4.4二進(jìn)制計(jì)數(shù)器狀態(tài)的譯碼若在一次狀態(tài)轉(zhuǎn)移中有2位或多位計(jì)數(shù)位同時(shí)變化，譯碼器輸出端可能會(huì)產(chǎn)生“尖峰脈沖”

——

功能性冒險(xiǎn)01234567012DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)40CLK

8位寄存器改進(jìn)：消除“毛刺”DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）modulo-mCounterDesignMethod1:UseSSIdevice

——ClockedSynchronousState-MachineDesignMethod2:UseMSIcounter

——Usingnbitbinarycounterasamodulomcounterm<2n

,采用清零法、置數(shù)法m>2n

,采用級(jí)聯(lián)法DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)Example1:usingthe’163asamodulo-11counter1.清零法S0S1S2S3S4S12S11S10S9S8S7S6S5S13S14S15計(jì)數(shù)到1010時(shí)，利用同步清零端強(qiáng)制為0000。DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）Example1:usingthe’163asamodulo-11counter1.清零法計(jì)數(shù)到1010時(shí)，利用同步清零端強(qiáng)制為000001010DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）Example1:usingthe’163asamodulo-11counter2.置數(shù)法S0S1S2S3S4S12S11S10S9S8S7S6S5S13S14S15計(jì)數(shù)到1111時(shí)，利用同步預(yù)置數(shù)端強(qiáng)制輸出為0101DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）Example1:usingthe’163asamodulo-11counter2.置數(shù)法計(jì)數(shù)到1111時(shí)，利用同步預(yù)置數(shù)端強(qiáng)制輸出為01011111101001DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）Example2:usingthe’163asanexcess-3decimalcounter。DecimalExcess-300011101002010130110401115100061001710108101191100UnusedCodeWords000000010010110111101111S0S1S2S3S4S12S11S10S9S8S7S6S5S13S14S15S30011S121100DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）Example2:usingthe’163asanexcess-3decimalcounter110000110DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）Example3:CascadingCounter(計(jì)數(shù)器的級(jí)聯(lián))思考：利用低4位的進(jìn)位RCO控制高4位的時(shí)鐘CLK行不行？①①②②111000000→1→100→1→1→1→0→0→0→0→1→1→1→0計(jì)數(shù)順序…0000111000010000…00001111DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）Example3:CascadingCounter(計(jì)數(shù)器的級(jí)聯(lián))思考：利用低4位的進(jìn)位RCO控制高4位的時(shí)鐘CLK行不行？11100→1→1→0→0→0→0→1→1→1→0①②0000→1計(jì)數(shù)順序…0000111000010000…00011111DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）Example3:CascadingCounter(計(jì)數(shù)器的級(jí)聯(lián))思考：如何利用低4位的進(jìn)位RCO控制高4位的時(shí)鐘CLK？11100→1→1→0→0→0→0→1→1→1→0①②0000→1計(jì)數(shù)順序…0000111000010000…00001111DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）模m計(jì)數(shù)器設(shè)計(jì)(m>2n

)

先進(jìn)行級(jí)聯(lián)，再整體置零或預(yù)置數(shù)例：用74x163構(gòu)造模193計(jì)數(shù)器兩片163級(jí)聯(lián)得8位二進(jìn)制計(jì)數(shù)器（0～255）

——采用整體清零法，0～192

——采用整體預(yù)置數(shù)法，63～255256－193＝63若m可以分解為：m=m1m2則可以分別實(shí)現(xiàn)m1和m2，然后再級(jí)聯(lián)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）6310=(00111111)2CLKCLRLDENPENTAQABQBCQCDQDRCO74x163CLKCLRLDENPENTAQABQBCQCDQDRCO74x16311001111+5VCLOCKCLR_LExample:模193計(jì)數(shù)器設(shè)計(jì)采用整體預(yù)置數(shù)法，63～255Q0Q1Q2Q3Q4Q5Q6Q7DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）6310=(00111111)2CLKCLRLDENPENTAQABQBCQCDQDRCO74x163CLKCLRLDENPENTAQABQBCQCDQDRCO74x16311001111+5VCLOCKCLR_LExample:模193計(jì)數(shù)器設(shè)計(jì)采用整體預(yù)置數(shù)法，63～255如何加上使能端？實(shí)現(xiàn)暫停(保持)

或繼續(xù)計(jì)數(shù)

問題：輸入端LD的優(yōu)先級(jí)高于ENP和ENT計(jì)數(shù)值無法停在255ENQ0Q1Q2Q3Q4Q5Q6Q7

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）6310=(00111111)2CLKCLRLDENPENTAQABQBCQCDQDRCO74x163CLKCLRLDENPENTAQABQBCQCDQDRCO74x16311001111+5VCLOCKCLR_LExample:模193計(jì)數(shù)器設(shè)計(jì)采用整體預(yù)置數(shù)法，63～255如何加上使能端？實(shí)現(xiàn)暫停(保持)

或繼續(xù)計(jì)數(shù)

問題：輸入端LD的優(yōu)先級(jí)高于ENP和ENT計(jì)數(shù)值無法停在255EN解決方法Q0Q1Q2Q3Q4Q5Q6Q7

ApplicationsofMSIcounters（MSI計(jì)數(shù)器應(yīng)用）CLKCLRLDENPENTAQABQBCQCDQDRCO74x163CLKCLRLDENPENTAQABQBCQCDQDRCO74x163CLOCKExam