基于89C51單片機(jī)的中英翻譯

我們的愛情，我們的理想，我們的未來，我們的成長，我們的幸福PAGE我們的愛情，我們的理想，我們的未來，我們的成長，我們的幸福（AT89C51中英文翻譯對照）Microcontrollersareusedinamultitudeofcommercialapplicationssuchasmodems,motor-controlsystems,airconditionercontrolsystems,automotiveengineandamongothers.Thehighprocessingspeedandenhancedperipheralsetofthesemicrocontrollersmakethemsuitableforsuchhigh-speedevent-basedapplications.However,thesecriticalapplicationdomainsalsorequirethatthesemicrocontrollersarehighlyreliable.Thehighreliabilityandlowmarketriskscanbeensuredbyarobusttestingprocessandapropertoolsenvironmentforthevalidationofthesemicrocontrollersbothatthecomponentandatthesystemlevel.IntelPlaformEngineeringdepartmentdevelopedanobject-orientedmulti-threadedtestenvironmentforthevalidationofitsAT89C51automotivemicrocontrollers.ThegoalsofthisenvironmentwasnotonlytoprovidearobusttestingenvironmentfortheAT89C51automotivemicrocontrollers,buttodevelopanenvironmentwhichcanbeeasilyextendedandreusedforthevalidationofseveralotherfuturemicrocontrollers.TheenvironmentwasdevelopedinconjunctionwithMicrosoftFoundationClasses(AT89C51).Thepaperdescribesthedesignandmechanismofthistestenvironment,itsinteractionswithvarioushardware/softwareenvironmentalcomponents,andhowtouseAT89C51.1.Introduction The8-bitAT89C51CHMOSmicrocontrollersaredesignedtohandlehigh-speedcalculationsandfastinput/outputoperations.MCS51microcontrollersaretypicallyusedforhigh-speedeventcontrolsystems.Commercialapplicationsincludemodems,motor-controlsystems,printers,photocopiers,airconditionercontrolsystems,diskdrives,andmedicalinstruments.TheautomotiveindustryuseMCS51microcontrollersinengine-controlsystems,airbags,suspensionsystems,andantilockbrakingsystems(ABS).TheAT89C51isespeciallywellsuitedtoapplicationsthatbenefitfromitsprocessingspeedandenhancedon-chipperipheralfunctionsset,suchasautomotivepower-traincontrol,vehicledynamicsuspension,antilockbraking,andstabilitycontrolapplications.Becauseofthesecriticalapplications,themarketrequiresareliablecost-effectivecontrollerwithalowinterruptlatencyresponse,abilitytoservicethehighnumberoftimeandeventdrivenintegratedperipheralsneededinrealtimeapplications,andaCPUwithaboveaverageprocessingpowerinasinglepackage.Thefinancialandlegalriskofhavingdevicesthatoperateunpredictablyisveryhigh.Onceinthemarket,particularlyinmissioncriticalapplicationssuchasanautopilotoranti-lockbrakingsystem,mistakesarefinanciallyprohibitive.Redesigncostscanrunashighasa$500K,muchmoreifthefixmeansbackannotatingitacrossaproductfamilythatsharethesamecoreand/orperipheraldesignflaw.Inaddition,fieldreplacementsofcomponentsisextremelyexpensive,asthedevicesaretypicallysealedinmoduleswithatotalvalueseveraltimesthatofthecomponent.Tomitigatetheseproblems,itisessentialthatcomprehensivetestingofthecontrollersbecarriedoutatboththecomponentlevelandsystemlevelunderworstcaseenvironmentalandvoltageconditions.Thiscompleteandthoroughvalidationnecessitatesnotonlyawell-definedprocessbutalsoaproperenvironmentandtoolstofacilitateandexecutethemissionsuccessfully.IntelChandlerPlatformEngineeringgroupprovidespostsiliconsystemvalidation(SV)ofvariousmicro-controllersandprocessors.Thesystemvalidationprocesscanbebrokenintothreemajorparts.Thetypeofthedeviceanditsapplicationrequirementsdeterminewhichtypesoftestingareperformedonthedevice.TheAT89C51providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afulldupleser-ialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsys-temtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheoscil-latordisablingallotherchipfunctionsuntilthenexthardwarereset.PinConfigurationsBlockDiagramPinDescriptionVCCSupplyvoltage.GNDGround.Port0Port0isan8-bitopen-drainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.Port0mayalsobeconfiguredtobethemultiplexedloworderaddress/databusduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.Port1Port1isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/so-urcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.Port2Port2isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcePort2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoPort2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,itusesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsdurinFlashprogrammingandverification.Port3Port3isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sou-rcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcePort3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow:PortPinAlternateFunctionsP3.0RXD(serialinputport)P3.1TXD(serialoutputport)P3.2INT0(externalinterrupt0)P3.3INT1(externalinterrupt1)P3.4T0(timer0externalinput)P3.5T1(timer1externalinput)P3.6WR(externaldatamemorywritestrobe)P3.7RD(externaldatamemoryreadstrobe)Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.RSTResetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.ALE/PROGAddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG)duringFlashprogramming.InnormaloperationALEisemittedataconstantrateof1/6theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduri-ngeachaccesstoexternalDataMemory.Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.PSENProgramStoreEnableisthereadstrobetoexternalprogrammemory.WhentheAT89C51isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.EA/VPPExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.EAshouldbestrappedtoVCCforinternalprogramexecutions.Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming,forpartsthatrequire12-voltVPP.XTAL1Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.XTAL2Outputfromtheinvertingoscillatoramplifier.OscillatorCharacteristicsXTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure1.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.IdleModeInidlemode,theCPUputsitselftosleepwhilealltheonchipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.Itshouldbenotedthatwhenidleisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecution,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.ToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyreset,theinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory.Figure1.OscillatorConnectionsFigure2.ExternalClockDriveConfigurationNote:C1,C2=30pF10pFforCrystals=40pF10pFforCeramicResonatorsPower-downModeInthepower-downmode,theoscillatorisstopped,andtheinstructionthatinvokespower-downisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepower-downmodeisterminated.Theonlyexitfrompower-downisahardwarereset.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.StatusofExternalPinsDuringIdleandPower-downModesModeProgramMemoryALEPSENPORT0PORT1PORT2PORT3IdleInternal11DataDataDataDataIdleExternal11FloatDataAddressDataPower-downInternal00DataDataDataDataPower-downExternal00FloatDataDataDataProgramMemoryLockBitsOnthechiparethreelockbitswhichcanbeleftunprogrammed(U)orcanbeprogrammed(P)toobtaintheadditionalfeatureslistedinthetablebelow.LockBitProtectionModesProgramLockBitsProtectionTypeLB1LB2LB31UUUNoprogramlockfeatures2PUUMOVCinstructionsexecutedfromexternalprogrammemoryaredisabledfrometchingcodebytesfrominternalmemory.3PPUSameasmode2,alsoverifyisdisabled4PPPSameasmode3,alsoexternalexecutionisdisabledWhenlockbit1isprogrammed,thelogiclevelattheEApinissampledandlatchedduringreset.Ifthedeviceispoweredupwithoutareset,thelatchinitializestoarandomvalue,andholdsthatvalueuntilresetisactivated.ItisnecessarythatthelatchedvalueofEAbeinagreementwiththecurrentlogiclevelatthatpininorderforthedevicetofunctionproperly.ProgrammingtheFlashTheAT89C51isnormallyshippedwiththeon-chipFlashmemoryarrayintheerasedstate(thatis,contents=FFH)andreadytobeprogrammed.Theprogramminginterfaceacceptseitherahigh-voltage(12-volt)oralow-voltage(VCC)programenablesignal.Thelow-voltageprogrammingmodeprovidesaconvenientwaytoprogramtheAT89C51insidetheuser’ssystem,whilethehigh-voltageprogrammingmodeiscompatiblewithconventionalthirdpartyFlashorEPROMprogrammers.TheAT89C51isshippedwitheitherthehigh-voltageorlow-voltageprogrammingmodeenabled.Therespectivetop-sidemarkinganddevicesignaturecodesarelistedinthefollowingtable.VPP=12VVPP=5VTop-SideMarkAT89C51xxxxyywwAT89C51xxxx-5yywwSignature(030H)=1EH(031H)=51H(032H)=FFH(030H)=1EH(031H)=51H(032H)=05HTheAT89C51codememoryarrayisprogrammedbyte-bybyteineitherprogrammingmode.Toprogramanynonblankbyteintheon-chipFlashMemory,theentirememorymustbeerasedusingtheChipEraseMode.ProgrammingAlgorithm:BeforeprogrammingtheAT89C51,theaddress,dataandcontrolsignalsshouldbesetupaccordingtotheFlashprogrammingmodetableandFigure3andFigure4.ToprogramtheAT89C51,takethefollowingsteps.1.Inputthedesiredmemorylocationontheaddresslines.2.Inputtheappropriatedatabyteonthedatalines.3.Activatethecorrectcombinationofcontrolsignals.4.RaiseEA/VPPto12Vforthehigh-voltageprogrammingmode.5.PulseALE/PROGoncetoprogramabyteintheFlasharrayorthelockbits.Thebyte-writecycleisself-timedandtypicallytakesnomorethan1.5ms.Repeatsteps1through5,changingtheaddressanddatafortheentirearrayoruntiltheendoftheobjectfileisreached.DataPolling:TheAT89C51featuresDataPollingtoindicatetheendofawritecycle.Duringawritecycle,anattemptedreadofthelastbytewrittenwillresultinthecomplementofthewrittendatumonPO.7.Oncethewritecyclehasbeencompleted,truedataarevalidonalloutputs,andthenextcyclemaybegin.DataPollingmaybeginanytimeafterawritecyclehasbeeninitiated.Ready/Busy:TheprogressofbyteprogrammingcanalsobemonitoredbytheRDY/BSYoutputsignal.P3.4ispulledlowafterALEgoeshighduringprogrammingtoindicateBUSY.P3.4ispulledhighagainwhenprogrammingisdonetoindicateREADY.ProgramVerify:IflockbitsLB1andLB2havenotbeenprogrammed,theprogrammedcodedatacanbereadbackviatheaddressanddatalinesforverification.Thelockbitscannotbeverifieddirectly.Verificationofthelockbitsisachievedbyobservingthattheirfeaturesareenabled.FlashProgrammingModesModeRSTPSENALE/PROGEA/VPPP2.6P2.7P3.6P3.7WriteCodeDataHLH/12VLHHHReadCodeDataHLHHLLHHWriteLockBit-1HLH/12VHHHHBit-2HLH/12VHHLLBit-3HLH/12VHLLLChipEraseHLH/12VHLLLReadSignatureByteHLHHLLLLNote:1.ChipEraserequiresa10msPROGpulse.Figure3.ProgrammingtheFlashFigure4.VerifyingtheFlashFlashProgrammingandVerificationWaveforms-High-voltageMode(VPP=12V)FlashProgrammingandVerificationWaveforms-Low-voltageMode(VPP=5V)ChipErase:TheentireFlasharrayiserasedelectricallybyusingthepropercombinationofcontrolsignalsandbyholdingALE/PROGlowfor10ms.Thecodearrayiswrittenwithall“1”s.Thechiperaseoperationmustbeexecutedbeforethecodememorycanbere-programmed.ReadingtheSignatureBytes:Thesignaturebytesarereadbythesameprocedureasanormalverificationoflocations030H,031H,and032H,exceptthatP3.6andP3.7mustbepulledtoalogiclow.Thevaluesreturnedareasfollows.(030H)=1EHindicatesmanufacturedbyAtmel(031H)=51Hindicates89C51(032H)=FFHindicates12Vprogramming(032H)=05Hindicates5VprogrammingProgrammingInterfaceEverycodebyteintheFlasharraycanbewrittenandtheentirearraycanbeerasedbyusingtheappropriatecombinationofcontrolsignals.Thewriteoperationcycleisselftimedandonceinitiated,willautomaticallytimeitselftocompletion.FlashProgrammingandVerificationCharacteristicsTA=0°Cto70°C,VCC=5.010%SymbolParameterMinMaxUnitsVPP(1)ProgrammingEnableVoltage11.512.5VIPP(1)ProgrammingEnableCurrent1.0mA1/tCLCLOscillatorFrequency324MHztAVGLAddressSetuptoPROGLow48tCLCLtGHAXAddressHoldAfterPROG48tCLCLtDVGLDataSetuptoPROGLow48tCLCLtGHDXDataHoldAfterPROG48tCLCLtEHSHP2.7(ENABLE)HightoVPP48tCLCLtSHGLVPPSetuptoPROGLow10μstGHSL(1)VPPHoldAfterPROG10μstGLGHPROGWidth1110μstAVQVAddresstoDataValid48tCLCLtELQVENABLELowtoDataValid48tCLCLtEHQZDataFloatAfterENABLE048tCLCLtGHBLPROGHightoBUSYLow1.0μstWCByteWriteCycleTime2.0msNote:1.Onlyusedin12-voltprogrammingmode.AbsoluteMaximumRatings*OperatingTemperature-55°Cto+125°CStorageTemperature-65°Cto+150°CVoltageonAnyPinwithRespecttoGround-1.0Vto+7.0VMaximumOperatingVoltage6.6VDCOutputCurrent15.0mADCCharacteristicsTA=-40°Cto85°C,VCC=5.0V20%(unlessotherwisenoted)SymbolParameterConditionMinMaxUnitsVILInputLow-voltage(ExceptEA)-0.50.2VCC-0.1VVIL1nputLow-voltage(EA)-0.50.2VCC-0.3VVIHiputHigh-voltage(ExceptXTAL1,RST)0.2VCC+0.9VCC+0.5VVIH1InputHigh-voltage(XTAL1,RST)0.7VCCVCC+0.5VVOLOutputLow-voltage(1)(Ports1,2,3)IOL=1.6mA0.45VVOL1OutputLow-voltage(1)(Port0,ALE,PSEN)IOL=3.2mA0.45VVOHOutputHigh-voltage(Ports1,2,3,ALE,PSEN)IOH=-60μA,VCC=5V10%2.4VIOH=-25μA0.75VCCVIOH=-10μA0.9VCCVVOH1OutputHigh-voltage(Port0inExternalBusMode)IOH=-800μA,VCC=5V10%2.4VIOH=-300μA,0.75VCCVIOH=-80μA,0.9VCCVIILLogical0InputCurrent(Ports1,2,3)VIN=0.45V-50μAITLLogical1to0TransitionCurrent(Ports1,2,3)VIN=2V,VCC=5V10%-650μAILIInputLeakageCurrent(Port0,EA)0.45<VIN<VCC10μARRSTResetPull-downResistor50300KCIOPinCapacitanceTestFreq.=1MHz,TA=25°C10pFICCPowerSupplyCurrentActiveMode,12MHz20mAIdleMode,12MHz5mAPower-downMode(2)VCC=6V100μAVCC=3V40μAACCharacteristicsUnderoperatingconditions,loadcapacitanceforPort0,ALE/PROG,andPSEN=100pF;loadcapacitanceforallotheroutputs=80pF.ExternalProgramandDataMemoryCharacteristicsSymbolParameterFrequency12MHzOscillator16to24MHzOscillatorUnitsMinMaxMinMax1/tCLCLOscillator024MHztLHLLALEPulseWidth1272tCLCL-4040nsnstAVLLAddressValidtoALELow43tCLCL-13nstLLAXAddressHoldAfterALELow48tCLCL-20nstLLIVALELowtoValidInstructionIn2334tCLCL-65nstLLPLALELowtoPSENLow43tCLCL-13nstPLPHPSENPulseWidth2053tCLCL-20nstPLIVPSENLowtoValidInstructionIn1453tCLCL-45nstPXIXInputInstructionHoldAfterPSEN00nstPXIZInputInstructionFloatAfterPSEN59tCLCL-10nstPXAVPSENtoAddressValid75tCLCL-8nstAVIVAddresstoValidInstructionIn3125tCLCL-55nstPLAZPSENLowtoAddressFloat1010nstRLRHRDPulseWidth4006tCLCL-100nstWLWHWRPulseWidth4006tCLCL-100nstRLDVRDLowtoValidDataIn2525tCLCL-90nstRHDXDataHoldAfterRD00nstRHDZDataFloatAfterRD972tCLCL-28nstLLDVALELowtoValidDataIn5178tCLCL-150nstAVDVAddresstoValidDataIn5859tCLCL-165nstLLWLALELowtoRDorWRLow2003003tCLCL-503tCLCL+50nstAVWLAddresstoRDorWRLow2034tCLCL-75nstQVWXDataValidtoWRTransition23tCLCL-20nstQVWHDataValidtoWRHigh4337tCLCL-120nstWHQXDataHoldAfterWR33tCLCL-20nstRLAZRDLowtoAddressFloat00nstWHLHRDorWRHightoALEHigh43123tCLCL-20nsExternalProgramMemoryReadCycleExternalDataMemoryReadCycleExternalDataMemoryWriteCycleExternalClockDriveWaveformsExternalClockDriveSymbolParameterMinMaxUnits1/tCLCLOscillatorFrequency024MHztCLCLClockPeriod41.6nstCHCXHighTime15nstCLCXLowTime15nstCLCHRiseTime20nstCHCLFallTimens20nsSerial(VCC=5.0V20%;LoadCapacitance=80pF)SymbolParameter12MHzOscVariableOscillatorUnitsUnitsMinMaxMinMaxtXLXLSerial1.012tCLCLμstQVXHOutputDataSetuptoClockRisingEdge70010tCLCL-133nstXHQXOutputDataHoldAfterClockRisingEdge502tCLCL-117nstXHDXInputDataHoldAfterClockRisingEdge00nstXHDVClockRisingEdgetoInputDataValid70010tCLCL-133nsShiftRegisterModeTimingWaveformsACTestingInput/OutputWaveforms(1)FloatWaveforms(1)Amicrocomputerinterfaceconvertsinformationbetweentwoforms.Outsidethemicrocomputertheinformationhandledbyanelectronicsystemexistsasaphysicalsignal,butwithintheprogram,itisrepresentednumerically.Thefunctionofanyinterfacecanbebrokendownintoanumberofoperationswhichmodifythedatainsomeway,sothattheprocessofconversionbetweentheexternalandinternalformsiscarriedoutinanumberofsteps.Ananalog-to-digitalconverter(ADC)isusedtoconvertacontinuouslyvariablesignaltoacorrespondingdigitalformwhichcantakeanyoneofafixednumberofpossiblebinaryvalues.Iftheoutputofthetransducerdoesnotvarycontinuously,noADCisnecessary.Inthiscasethesignalconditioningsectionmustconverttheincomingsignaltoaformwhichcanbeconnecteddirectlytothenextpartoftheinterface,theinput/outputsectionofthemicrocomputeritself.Outputinterfacestakeasimilarform,theobviousdifferencebeingthatheretheflowofinformationisintheoppositedirection;itispassedfromtheprogramtotheoutsideworld.Inthiscasetheprogrammaycallanoutputsubroutinewhichsupervisestheoperationoftheinterfaceandperformsthescalingnumberswhichmaybeneededforadigital-to-analogconverter(DAC).Thissubroutinepassesinformationinturntoanoutputdevicewhichproducesacorrespondingelectricalsignal,whichcouldbeconvertedintoanalogformusingaDAC.Finallythesignalisconditioned(usuallyamplified)toaformsuitableforoperatinganactuator.Thesignalsusedwithinmicrocomputercircuitsarealmostalwaystoosmalltobeconnecteddirectlytothe“outsideworld”andsomekindofinterfacemustbeusedtotranslatethemtoamoreappropriateform.Thedesignofsectionofinterfacecircuitsisoneofthemostimportanttasksfacingtheengineerwishingtoapplymicrocomputers.Wehaveseenthatinmicrocomputersinformationisrepresentedasdiscretepatternsofbits;thisdigitalformismostusefulwhenthemicrocomputeristobeconnectedtoequipmentwhichcanonlybeswitchedonoroff,whereeachbitmightrepresentthestateofaswitchoractuator.Tosolvereal-worldproblems,amicrocontrollermusthavemorethanjustaCPU,aprogram,andadatamemory.Inaddition,itmustcontainhardwareallowingtheCPUtoaccessinformationfromtheoutsideworld.OncetheCPUgathersinformationandprocessesthedata,itmustalsobeabletoeffectchangeonsomeportionoftheoutsideworld.Thesehardwaredevices,calledperipherals,aretheCPU’swindowtotheoutside.ThemostbasicformofperipheralavailableonmicrocontrollersisthegeneralpurposeI70port.EachoftheI/Opinscanbeusedaseitheraninputoranoutput.Thefunctionofeachpinisdeterminedbysettingorclearingcorrespondingbitsinacorrespondingdatadirectionregisterduringtheinitializationstageofaprogram.EachoutputpinmaybedriventoeitheralogiconeoralogiczerobyusingCPUinstructionstopinmaybeviewed(orread.)bytheCPUusingprograminstructions.SometypeofserialunitisincludedonmicrocontrollerstoallowtheCPUtocommunicatebit-seriallywithexternaldevices.Usingabitserialformatinsteadofbit-parallelformatrequiresfewerI/Opinstoperformthecommunicationfunction,whichmakesitlessexpensive,butslower.Serialtransmissionsareperformedeithersynchronouslyorasynchronously.單片機(jī)廣泛應(yīng)用于商業(yè)：諸如調(diào)制解調(diào)器，電動機(jī)控制系統(tǒng)，空調(diào)控制系統(tǒng)，汽車發(fā)動機(jī)和其他一些領(lǐng)域。這些單片機(jī)的高速處理速度和增強(qiáng)型外圍設(shè)備集合使得它們適合于這種高速事件應(yīng)用場合。然而，這些關(guān)鍵應(yīng)用領(lǐng)域也要求這些單片機(jī)高度可靠。健壯的測試環(huán)境和用于驗證這些無論在元部件層次還是系統(tǒng)級別的單片機(jī)的合適的工具環(huán)境保證了高可靠性和低市場風(fēng)險。Intel平臺工程部門開發(fā)了一種面向?qū)ο蟮挠糜隍炞C它的AT89C51汽車單片機(jī)多線性測試環(huán)境。這種環(huán)境的目標(biāo)不僅是為AT89C51汽車單片機(jī)提供一種健壯測試環(huán)境，而且開發(fā)一種能夠容易擴(kuò)展并重復(fù)用來驗證其他幾種將來的單片機(jī)。開發(fā)的這種環(huán)境連接了AT89C51。本文討論了這種測試環(huán)境的設(shè)計和原理，它的和各種硬件、軟件環(huán)境部件的交互性，以及如何使用AT89C51。1介紹8位AT89C51CHMOS工藝單片機(jī)被設(shè)計用于處理高速計算和快速輸入/輸出。MCS51單片機(jī)典型的應(yīng)用是高速事件控制系統(tǒng)。商業(yè)應(yīng)用包括調(diào)制解調(diào)器，電動機(jī)控制系統(tǒng)，打印機(jī)，影印機(jī)，空調(diào)控制系統(tǒng)，磁盤驅(qū)動器和醫(yī)療設(shè)備。汽車工業(yè)把MCS51單片機(jī)用于發(fā)動機(jī)控制系統(tǒng)，懸掛系統(tǒng)和反鎖制動系統(tǒng)。AT89C51尤其很好適用于得益于它的處理速度和增強(qiáng)型片上外圍功能集，諸如：汽車動力控制，車輛動態(tài)懸掛，反鎖制動和穩(wěn)定性控制應(yīng)用。由于這些決定性應(yīng)用，市場需要一種可靠的具有低干擾潛伏響應(yīng)的費(fèi)用-效能控制器，服務(wù)大量時間和事件驅(qū)動的在實時應(yīng)用需要的集成外圍的能力，具有在單一程序包中高出平均處理功率的中央處理器。擁有操作不可預(yù)測的設(shè)備的經(jīng)濟(jì)和法律風(fēng)險是很高的。一旦進(jìn)入市場，尤其任務(wù)決定性應(yīng)用諸如自動駕駛儀或反鎖制動系統(tǒng)，錯誤將是財力上所禁止的。重新設(shè)計的費(fèi)用可以高達(dá)500K美元，如果產(chǎn)品族享有同樣內(nèi)核或外圍設(shè)計缺陷的話，費(fèi)用會更高。另外，部件的替代品領(lǐng)域是極其昂貴的，因為設(shè)備要用來把模塊典型地焊接成一個總體的價值比各個部件高幾倍。為了緩和這些問題，在最壞的環(huán)境和電壓條件下對這些單片機(jī)進(jìn)行無論在部件級別還是系統(tǒng)級別上的綜合測試是必需的。IntelChandler平臺工程組提供了各種單片機(jī)和處理器的系統(tǒng)驗證。這種系統(tǒng)的驗證處理可以被分解為三個主要部分。系統(tǒng)的類型和應(yīng)用需求決定了能夠在設(shè)備上執(zhí)行的測試類型。AT89C51提供以下標(biāo)準(zhǔn)功能：4k字節(jié)FLASH閃速存儲器，128字節(jié)內(nèi)部RAM，32個I/O口線，2個16位定時/計數(shù)器，一個5向量兩級中斷結(jié)構(gòu)，一個全雙工串行通信口，片內(nèi)振蕩器及時鐘電路。同時，AT89C51降至0Hz的靜態(tài)邏輯操作，并支持兩種可選的節(jié)電工作模式?？臻e方式體制CPU的工作，但允許RAM，定時/計數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器體制工作并禁止其他所有不見工作直到下一個硬件復(fù)位。AT89C51方框圖引腳功能說明·Vcc：電源電壓·GND：地·P0口：P0口是一組8位漏極開路型雙向I/O口，也即地址/數(shù)據(jù)總線復(fù)用。作為輸出口用時，每位能吸收電流的方式驅(qū)動8個TTL邏輯門電路，對端口寫“1”可作為高阻抗輸入端用。在訪問外部數(shù)據(jù)存儲器或程序存儲器時，這組口線分時轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問期間激活內(nèi)部上拉電阻。在Flash編程時，P0口接受指令字節(jié)，而在程序校驗時，輸出指令字節(jié)，校驗時，要求外接上拉電阻?！1口：P1是一個帶內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路。對端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時可作輸入口。作為輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。Flash編程和程序校驗期間，P1接受低8位地址。·P2口：P2是一個帶有內(nèi)部上拉電阻的8位雙向I/O口，P2的輸出緩沖級可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路。對端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時可作輸入口。作為輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。在訪問外部程序存儲器或16位四肢的外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX@DPTR指令）時，P2口送出高8位地址數(shù)據(jù)，在訪問8位地址的外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX@RI指令）時，P2口線上的內(nèi)容（也即特殊功能寄存器（SFR）區(qū)中R2寄存器的內(nèi)容），在整個訪問期間不改變。Flash編程和程序校驗時，P2也接收高位地址和其他控制信號?！3口：P3是一個帶有內(nèi)部上拉電阻的8位雙向I/O口，P3的輸出緩沖級可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路。對端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時可作輸入口。作為輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。P3口除了作為一般的I/O口線外，更重要的用途是它的第二功能，如下所示：端口引腳第二功能P3.0RXD(串行輸入口)P3.1TXD(串行輸出口)P3.2INT0(外中斷0)P3.3INT1(外中斷1)P3.4T0(定時/計數(shù)器0)P3.5T1(定時/計數(shù)器1)P3.6WR(外部數(shù)據(jù)存儲器寫選通)P3.7RD(外部數(shù)據(jù)存儲器讀選通)P3口還接收一些用于Flash閃速存儲器編程和程序校驗的控制信號?！ST：復(fù)位輸入。當(dāng)振蕩器工作時，RST引腳出現(xiàn)兩個機(jī)器周期以上高電平將使單片機(jī)復(fù)位?！LE/PROG：當(dāng)訪問外部程序存儲器或數(shù)據(jù)存儲器時，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲器，ALE仍以時鐘振蕩頻率的1/6輸出固定的正脈沖信號，因此它可對外輸出時鐘或用于定時目的。要注意的是，每當(dāng)訪問外部數(shù)據(jù)存儲器時將跳過一個ALE脈沖。對Flash存儲器編程期間，該引腳還用于輸入編程脈沖（PROG）。如有必要，可通過對特殊功能寄存器（SFR）區(qū)中的8EH單元D0位置位，可禁止ALE操作。該位置位后，只有一條MOVX和MOVC指令A(yù)LE才會被激活。此外，該引腳會被微弱拉高，單片機(jī)執(zhí)行外部程序時，應(yīng)設(shè)置ALE無效?！SEN：程序存儲允許輸出是外部程序存儲器的讀選通型號，當(dāng)89C51由外部存儲器取指令（或數(shù)據(jù)）時，每個機(jī)器周期兩次PSEN有效，即輸出兩個脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲器，這兩次有效的PSEN信號不出現(xiàn)?！A/VPP：外部訪問允許。欲使CPU僅訪問外部程序存儲器（地址為0000H—FFFFH），EA端必須保持低電平（接地）。需注意的是：如果加密位LB1被編程，復(fù)位時內(nèi)部會鎖存EA端狀態(tài)。如EA端為高電平（接Vcc端），CPU則執(zhí)行內(nèi)部程序存儲器中的指令。Flash存儲器編程時，該引腳加上+12v的編程允許電源Vpp，當(dāng)然這必須是該器件使用12v編程電壓Vpp?！TAL1：振蕩器反相放大器及內(nèi)部時鐘發(fā)生器的輸入端?！TAL2：振蕩器反相放大器的輸出端·時鐘振蕩器：89C51中有一個用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入端和輸出端。這個放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器，振蕩電路參見圖5。外接石英晶體或陶瓷諧振器及電容C1、C2接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。對外接電容C1、C2雖沒有十分嚴(yán)格的要求，但電容容量的大小會輕微影響振蕩頻率的高低、振蕩器