集成電路講義

《集成電路分析與設(shè)計(jì)》課程主要介紹什么內(nèi)容?CMOS數(shù)字集成電路(CMOSdigitalIC)IC的發(fā)展歷史及現(xiàn)狀(HistoryofIC)IC設(shè)計(jì)流程和方法(DesignprocessandMethodology)IC制造工藝技術(shù)(Fabricationprocess)ICEDA（CAD）工具使用(EDAtools)CMOS反相器設(shè)計(jì)(CMOSInverter)CMOS組合邏輯門設(shè)計(jì)(CombinationalLogicCircuit)CMOS時(shí)序邏輯電路設(shè)計(jì)(SequentialLogicCircuit)IC版圖設(shè)計(jì)(Layout)IC仿真技術(shù)(Simulation)存儲器電路設(shè)計(jì)介紹(MemoryCircuits)模擬IC設(shè)計(jì)介紹(AnalogIC)《集成電路分析與設(shè)計(jì)》課程信息課程性質(zhì)：是一門專業(yè)基礎(chǔ)課程主要介紹CMOS數(shù)字集成電路設(shè)計(jì)的基礎(chǔ)知識共40課時(shí)（32理論課時(shí)+8實(shí)驗(yàn)課時(shí)）完成4個(gè)實(shí)驗(yàn)對準(zhǔn)備從事IC行業(yè)的學(xué)生來講，本課程只是一個(gè)基礎(chǔ)，還需要繼續(xù)深入學(xué)習(xí)更多關(guān)于IC設(shè)計(jì)的知識，如數(shù)字IC深入，模擬IC，RFIC等。實(shí)驗(yàn)內(nèi)容（共8學(xué)時(shí)）實(shí)驗(yàn)一（2學(xué)時(shí)）反相器電路設(shè)計(jì)（SimulationandLayout）實(shí)驗(yàn)二（2學(xué)時(shí)）NAND電路設(shè)計(jì)（SimulationandLayout）實(shí)驗(yàn)三（2學(xué)時(shí)）AND電路設(shè)計(jì)（SimulationandLayout）實(shí)驗(yàn)四（2學(xué)時(shí)）D觸發(fā)器電路設(shè)計(jì)（SimulationandLayout）Project（選作內(nèi)容）完成一個(gè)44SRAM芯片的設(shè)計(jì)3人一組項(xiàng)目過程：A期中OralpresentationB期末OralpresentationC項(xiàng)目報(bào)告書一份D3人項(xiàng)目成績相同GradingPolicy課堂提問和作業(yè)10%實(shí)驗(yàn)20%考試（開卷）70%規(guī)則：（1）1個(gè)問題和4次作業(yè)，每次/個(gè)2分，共10分；（2）每個(gè)實(shí)驗(yàn)完成得5分，共20分；（3）點(diǎn)名1次不到，10分沒了；（4）抄作業(yè)，抄實(shí)驗(yàn)報(bào)告，相應(yīng)分?jǐn)?shù)沒了；（5）請假規(guī)則：必須有正規(guī)請假手續(xù)和課前請假。

本課程推薦書目

教材中文版周潤德等譯，數(shù)字集成電路設(shè)計(jì)透視第二版，電子工業(yè)出版社(JanM.Rabaey,etal.DigitalIntegratedCircuits,2nde,PrenticeHall,2004)參考書Sung-Mo(Steve)Kang,YusufLeblebici,CMOSDigitalIntegratedCircuitsAnalysis&Design,3rdEdition,McGraw-Hill2003R.JacobBaker,CMOSCircuitDesign,Layout,andsimulation,3rdEdition,Wiley,2010韓雁，集成電路設(shè)計(jì)CAD/EDA工具實(shí)用教程，機(jī)械工業(yè)出版社，2010

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模擬集成電路Razavi，模擬CMOS集成電路設(shè)計(jì)，清華大學(xué)出版社，2005通用參考書（Bible）威斯特，CMOS超大規(guī)模集成電路設(shè)計(jì)，第三版，中國電力出版社幾個(gè)常見縮略詞CMOS(complementarymetaloxidesemiconductor)IC(integratedcircuit)VLSI(verylargescaleintegrated)ULSI(ultra-largescaleintegrated)MOSFET(metaloxidesemiconductorfieldeffecttransistors)SPICE(simulationprogramwithintegratedcircuitemphasis)認(rèn)識集成電路和集成電路設(shè)計(jì)為什么需要集成電路？與以前的集成電路設(shè)計(jì)相比，為什么現(xiàn)在的集成電路設(shè)計(jì)出現(xiàn)了不同以及現(xiàn)在的集成電路設(shè)計(jì)遇到了哪些新的挑戰(zhàn)？未來，集成電路將如何發(fā)展？為什么需要集成電路?Integrationreducesdevicesize（減小尺寸）Laptop,iPod,mp3,cellphone,...Integrationimprovesthedesign（提高性能）higherspeed;lowerpowerconsuption;morereliable.Integrationreducesmanufacturingcost（降低成本）BOM(BoardofMaterials)costreducesMassICproductionreducescostElectronicsIndustryDesign,fab,applicationEducationSoftwareCommunication/NetworkingFabcost:$2-$3billionDrivingforceofworldeconomyLargeinvestment:fab,packaging,design,EDAPentium?4“Northwood”55Mtransistors/2-2.5GHzL=0.13μmMoore’sLaw(1965)GordonMoore–IntelFounder“Thenumberoftransistorsonachipdoubledevery18to24months.”Electronics,April19,1965.GordonMooreIntelCo-FounderandChairmainEmeritusImagesource:IntelCorporationInformationRevolutionElectronicsystemincars.Electronicfinancialsystem:e-banking,e-money,e-stock,RFIDlablePersonalcomputing/entertainmentMedicalelectronicsystems.Internet:routers,firewalls,servers,storagesElectroniclibrary(Google,...)DVDR/W,HDTV,InteractiveTVIngeneral,consumerelectronicsetc...ChallengesofICDesignComplexity:Multi-milliontransistorsonasinglechip(smallersize/fasterspeed)Multipleandconflictingspecificationsforhighperformance(power/speed/throughput)Competition:ShortdesigntimeDesignTools:Multipletoolsinvolved,ComplexdesignflowAnalogBasebandDigitalBaseband(DSP+MCU)PowerManagementSmallSignalRFPowerRFRelatedtoICJobs?Layoutdesigners?Circuitdesigners(Digital/Analog/RF)?Architects?Test/Verificationengineers?Fabricationengineers?Systemdesigners(SoC)?CADtoolprogrammersEmbeddedSystemdevelopersSoftwareprogrammersTheTransistorRevolutionFirsttransistorBellLabs,1947J.Bardeen,W.Shockley,andW.Brattain(1956NobelprizeLaureate)1958年J.Kilby（TI）研制成功第一個(gè)集成電路1959年R.Noyce（Fairchild）第一個(gè)利用平面工藝制成集成電路TheFirstIntegratedCircuitsTheFirstIntegratedCircuitsBipolarlogic1960’sECL3-inputGateMotorola1966FirstcommercialIClogicgates–Fairchild1960TTL–1962intothe1990’sECL–1974intothe1980’s

Intel4004Micro-Processor19702300transistors~1MHzoperationIntelPentium(IV)microprocessorPentium?4“Northwood”CommercialProduction:Year2001L=0.13μm6MLCuLow-kFC-PGA2MOSFETTechnologyMOSFETtransistor-Lilienfeld(Canada)in1925andHeil(England)in1935CMOS–1960’s,butplaguedwithmanufacturingproblems(usedinwatchesduetotheirpowerlimitations)PMOSin1960’s(calculators)NMOSin1970’s(4004,8080)–forspeedCMOSin1980’s–preferredMOSFETtechnologybecauseofpowerbenefitsBiCMOS,Gallium-Arsenide,Silicon-GermaniumSOI,Copper-LowK,strainedsilicon,High-kgateoxide...WorldwideSemiconductorRevenueSource:ISSCC2003G.Moore“Noexponentialisforever,but‘forever’canbedelayed”1’’Waferin1964vs.300mm(12”)Waferin2003IBMPowerPC970(130nm)20031.8Ghz58M118mm2ApplePowerG5,thefastestPCin2003,hasdualPPC970CPUTwochipsyouareseeingtodayMicroprocessorASIC(ApplicationSpecificIC)State-of-theArt:LeadMicroprocessorsState-of-theArt:LeadMicroprocessors(uptodate)

Pentium4180nm(2001)1.7GHz42Mtransistors217mm2Pentium4130nm(2003)3.2GHz55MTransistors131mm2Pentium490nm(2004)3.4Hz125MTransistors112mm2Pentiumon65nm(2005/2006)250Million

Pentiumon45nm(2007)400to500Million

Freq(HZ)TransistorsDiesizemm2Power

DateServerIBMPower4+1.7G180M267N/A2003Itanium21.5G410M374130W2003IBMPower52G276M389

N/A

2004/2PCIBMPowerPC9701.8G58M11842W2003/6Pentium43.2G55M13182W2003/6AMDAthlon642.2G105M19289W2003/9Pentium4(Prescott)3.4G125M112103W2004/2(Alluse0.13umtechnologyexceptPentium4–Prescott,whichuses90nmtech)State-of-theArt:LeadMicroprocessors(uptodate)300mmwaferandPentium4IC.PhotoscourtesyofIntel.WhatADigitalDesignerNeedstoKnow...

“MicroscopicProblems”?Ultra-highspeeddesignInterconnect?Noise,Crosstalk?Reliability,Manufacturability?PowerDissipation?Clockdistribution.

“MacroscopicIssues”?Time-to-Market?MillionsofGates?High-LevelAbstractions?Reuse&IPAvailability?systemsonachip(SoC)

?Predictability?etc.>95%如何設(shè)計(jì)一個(gè)集成電路？TheVLSIdesignprocess工程的藝術(shù)Maybepartoflargerproductdesign.Majorlevelsofabstraction:specificationarchitecturelogicdesigncircuitdesignlayoutdesignMajorSegmentsofICIndustryFablessDesignHousesEDAToolsCompaniesDesignServiceCompaniesLibrary&IPProvidersDedicatedICManufacturers(Foundry)Post:EDA:ElectronicDesignAutomationIP:siliconIntellectualPropertyIDM:IntegratedDeviceManufacturerIntegratedservicePackaging&TestingHousesASICDesignStylesFullCustomDesignFlowCircuitiscreatedbycomposingatransistornetlistSPICEsimulationisperformedtoverifythecircuitKnownas“capture-and-simulate”paradigmLayoutismostlydonemanuallyPopularforhigh-performancemicroprocessors&memoriesCell-BasedSynthesisFlowDesignisfirstdescribedbyHardwareDescriptionLanguage(e.g.,VerilogandVHDL)Basedonacelllibrary,netlistiscreatedbysynthesistoolsKnownas“describe-and-synthesize”paradigmLayoutcanbedonethroughautomatictoolsDetailedCustomDesignFlowBlockSpecification(FiniteStateMachine,ArithmeticExpression,BooleanExpression)LogicDesignGate-LevelNetlistTransistorNetlistTechnologyMappingSPICESimulationSPICEModelLayoutDesignLayoutLayoutRulesDesignRuleChecking(DRC)Layoutvs.SchematicCheck(LVS)Parasitic(orwiring)RCextractionPost-LayoutSPICESimulationCheckifSPECismet?Ifyes,done.Otherwise,gobacktooptimizethedesignASimpleExample FunctionalityOne-bitbinaryfull-adderTechnology1mmn-wellCMOStechnologySpeedInputtooutputdelay<5nsArea<3000mm2PowerDissipation<1mWat5voltsand200MHzFull-adderABSumCarry_outSum=A⊕B⊕C=ABC+ABC+ABC+ACBCarry_out=AB+BC+CA(majorityfunction)BooleanDescriptionCLogicDesignLogicminimizationtrick:Thecarry_outsignalisusedtorealizethefunctionofsignalsum

inordertoreducetheoverallcircuitsize.Today’slogicsynthesistools(suchasDesignCompiler)incorporatingsomeadvancedalgorithms,isabletoperformautomaticlogicminimization.x=Carry_out#of‘1’sInA,B,C

Carry_out

Sum012300110101(A+B+C)x=>exactlyoneofA,B,Cis‘1’Transistor-LevelSchematicTechnologymappingManysimpleANDORgatesaremergedintoacomplexgate(oracellinthecelllibrary)TransistoraspectratiopMOS(W/L)isusuallylargerthannMOS(W/L),e.g.,2:1xyxyx=(AB+BC+CA)y=(A+B+C)x+ABC)InitialLayoutPost-layoutSPICEsimulationincludesthe“parasiticresistance&capacitance”ismoreaccuratethanthepre-layoutsimulation(pre-sim)Ratioofchannelwidths2:1I/OSimulationWaveformsPropagationtimetPHLortPLHasdefinedaboveLow-to-highpropagationtime（傳播延時(shí)）tPLH=8.2ns!Gottogobacktooptimizethedesign!!!C(Carry_in)SumOptimizedLayoutTransistorSizingchangestheaspectratios(W/L)ofselectedtransistorsAlargeraspectratiomayleadtoahigherspeedWireSizingisalsomorerecentlyp