一個(gè)簡單的RTL同步FIFO設(shè)計(jì)

一個(gè)簡單的RTL同步FIFO設(shè)計(jì)FIFO是FPGA設(shè)計(jì)中最有用的模塊之一。FIFO在模塊之間提供簡單的握手和同步機(jī)制，是設(shè)計(jì)人員將數(shù)據(jù)從一個(gè)模塊傳輸?shù)搅硪粋€(gè)模塊的常用選擇。在這篇文章中，展示了一個(gè)簡單的RTL同步FIFO，可以直接在自己的設(shè)計(jì)中配置和使用它，該設(shè)計(jì)是完全可綜合的。為什么要自己設(shè)計(jì)FIFO那么，為什么呢？網(wǎng)上有很多關(guān)于FIFO的Verilog/VHDL代碼的資源，過去，我自己也使用過其中的一些。但令人沮喪的是，它們中的大多數(shù)都存在問題，尤其是在上溢出和下溢出條件下。所以想一勞永逸地解決這些問題。FIFO規(guī)格性能同步，單時(shí)鐘?；诩拇嫫鞯腇IFO，適用于中小型FIFO。Full、Empty、Almost-full、Almost-empty標(biāo)志。完全可配置的數(shù)據(jù)寬度、深度和標(biāo)志。完全可綜合的系統(tǒng)Verilog代碼。

/*===============================================================================================================================

Design

:

Single-clock

Synchronous

FIFO

Description

:

Fully

synthesisable,

configurable

Single-clock

Synchronous

FIFO

based

on

registers.

-

Configurable

Data

width.

-

Configurable

Depth.

-

Configurable

Almost-full

and

Almost-empty

signals.

===============================================================================================================================*/module

my_fifo

#(

parameter

DATA_W

=

4

,

//

Data

width

parameter

DEPTH

=

8

,

//

Depth

of

FIFO

parameter

UPP_TH

=

4

,

//

Upper

threshold

to

generate

Almost-full

parameter

LOW_TH

=

2

//

Lower

threshold

to

generate

Almost-empty

)

(

input

clk

,

//

Clock

input

rstn

,

//

Active-low

Synchronous

Reset

input

i_wren

,

//

Write

Enable

input

[DATA_W

-

1

:

0]

i_wrdata

,

//

Write-data

output

o_alm_full

,

//

Almost-full

signal

output

o_full

,

//

Full

signal

input

i_rden

,

//

Read

Enable

output

[DATA_W

-

1

:

0]

o_rddata

,

//

Read-data

output

o_alm_empty

,

//

Almost-empty

signal

output

o_empty

//

Empty

signal

);/*-------------------------------------------------------------------------------------------------------------------------------

Internal

Registers/Signals-------------------------------------------------------------------------------------------------------------------------------*/logic

[DATA_W

-

1

:

0]

data_rg

[DEPTH]

;

//

Data

arraylogic

[$clog2(DEPTH)

-

1

:

0]

wrptr_rg

;

//

Write

pointerlogic

[$clog2(DEPTH)

-

1

:

0]

rdptr_rg

;

//

Read

pointerlogic

[$clog2(DEPTH)

:

0]

dcount_rg

;

//

Data

counter

logic

wren_s

;

//

Write

Enable

signal

generated

iff

FIFO

is

not

fulllogic

rden_s

;

//

Read

Enable

signal

generated

iff

FIFO

is

not

emptylogic

full_s

;

//

Full

signallogic

empty_s

;

//

Empty

signal/*-------------------------------------------------------------------------------------------------------------------------------

Synchronous

logic

to

write

to

and

read

from

FIFO-------------------------------------------------------------------------------------------------------------------------------*/always

@

(posedge

clk)

begin

if

(!rstn)

begin

data_rg

<=

'{default:

'0}

;

wrptr_rg

<=

0

;

rdptr_rg

<=

0

;

dcount_rg

<=

0

;

end

else

begin

ready_rg

<=

1'b1

;

/*

FIFO

write

logic

*/

if

(wren_s)

begin

data_rg

[wrptr_rg]

<=

i_wrdata

;

//

Data

written

to

FIFO

if

(wrptr_rg

==

DEPTH

-

1)

begin

wrptr_rg

<=

0

;

//

Reset

write

pointer

end

else

begin

wrptr_rg

<=

wrptr_rg

+

1

;

//

Increment

write

pointer

end

end

/*

FIFO

read

logic

*/

if

(rden_s)

begin

if

(rdptr_rg

==

DEPTH

-

1)

begin

rdptr_rg

<=

0

;

//

Reset

read

pointer

end

else

begin

rdptr_rg

<=

rdptr_rg

+

1

;

//

Increment

read

pointer

end

end

/*

FIFO

data

counter

update

logic

*/

if

(wren_s

&&

!rden_s)

begin

//

Write

operation

dcount_rg

<=

dcount_rg

+

1

;

end

else

if

(!wren_s

&&

rden_s)

begin

//

Read

operation

dcount_rg

<=

dcount_rg

-

1

;

end

endend/*-------------------------------------------------------------------------------------------------------------------------------

Continuous

Assignments-------------------------------------------------------------------------------------------------------------------------------*///

Full

and

Empty

internalassign

full_s

=

(dcount_rg

==

DEPTH)

?

1'b1

:

0

;assign

empty_s

=

(dcount_rg

==

0

)

?

1'b1

:

0

;//

Write

and

Read

Enables

internalassign

wren_s

=

i_wren

&

!full_s

;

assign

rden_s

=

i_rden

&

!empty_s

;//

Full

and

Empty

to

outputassign

o_full

=

full_s