計(jì)算機(jī)組織與結(jié)構(gòu)：版7-10_Instruction Sets characteristics

1、1,William Stallings Computer Organization and Architecture7th Edition,Chapter 10 Instruction Sets: Characteristics and Functions,2/40,Key terms (24),accumulator, address arithmetic shift, logical shift, rotate big endian, little endian, bi-endian branch, conditional branch, jump, skip instruction se

2、t, machine instruction operand, operation, stack, push, pop, packed decimal, procedure call， procedure return， reentrant procedure， reverse Polish notation,3/40,What is an Instruction Set?,The complete collection of instructions that are understood by a CPU Machine Code Binary Usually represented by

3、 assembly codes,4/40,Elements of an Instruction,Operation code (Op code) Do this Source Operand reference To this Result Operand reference Put the answer here Next Instruction Reference When you have done that, do this.,5/40,Where have all the Operands Gone?,Long time passing. (If you dont understan

4、d, youre too young!) Main memory (or virtual memory or cache) CPU register I/O device,6/40,Instruction Cycle State Diagram,7/40,Instruction Representation,In machine code each instruction has a unique bit pattern For human consumption (well, programmers anyway) a symbolic representation is used e.g.

5、 ADD, SUB, LOAD Operands can also be represented in this way ADD A,B,8/40,Simple Instruction Format,9/40,Instruction Types,Data processing Data storage (main memory) Data movement (I/O) Program flow control,10/40,Number of Addresses (a),3 addresses Operand 1, Operand 2, Result a = b + c; May be a fo

6、rth - next instruction (usually implicit) Not common Needs very long words to hold everything Implicit 英音：implisit 暗示的，含蓄的,11/40,Number of Addresses (b),2 addresses One address doubles as operand and result a = a + b Reduces length of instruction Requires some extra work Temporary storage to hold so

7、me results,12/40,Number of Addresses (c),1 address Implicit second address Usually a register (accumulator) Common on early machines,13/40,Number of Addresses (d),0 (zero) addresses All addresses implicit Uses a stack e.g. push a push b add pop c c = a + b,14/40,How Many Addresses,More addresses Mor

8、e complex (powerful?) instructions More registers Inter-register operations are quicker Fewer instructions per program Fewer addresses Less complex (powerful?) instructions More instructions per program Faster fetch/execution of instructions,15/40,Design Decisions (1),Operation repertoire How many o

9、ps? What can they do? How complex are they? Data types Instruction formats Length of op code field Number of addresses Repertoire 英音：reptw: 保留曲目，全部曲目,16/40,Design Decisions (2),Registers Number of CPU registers available Which operations can be performed on which registers? Addressing modes (later)

10、RISC v CISC,17/40,Types of Operand,Addresses Numbers Integer/floating point Characters ASCII etc. Logical Data Bits or flags (Aside: Is there any difference between numbers and characters? Ask a C programmer!),18/40,Pentium Data Types,8 bit Byte 16 bit word 32 bit double word 64 bit quad word quad 英

11、音：kwd 四倍 Addressing is by 8 bit unit A 32 bit double word is read at addresses divisible by 4,19/40,Specific Data Types,General - arbitrary binary contents Integer - single binary value Ordinal - unsigned integer Unpacked BCD - One digit per byte Packed BCD - 2 BCD digits per byte Near Pointer - 32

12、bit offset within segment Bit field Byte String Floating Point,20/40,Pentium Numeric Data Formats,21/40,PowerPC Data Types,8 (byte), 16 (halfword), 32 (word) and 64 (doubleword) length data types Some instructions need operand aligned on 32 bit boundary Can be big- or little-endian Fixed point proce

13、ssor recognises: Unsigned byte, unsigned halfword, signed halfword, unsigned word, signed word, unsigned doubleword, byte string (128 bytes) Floating point IEEE 754 Single or double precision,22/40,Types of Operation,Data Transfer Arithmetic Logical Conversion I/O System Control Transfer of Control,

14、23/40,Data Transfer,Specify Source Destination Amount of data May be different instructions for different movements e.g. IBM 370 Or one instruction and different addresses e.g. VAX,24/40,Arithmetic,Add, Subtract, Multiply, Divide Signed Integer Floating point ? May include Increment (a+) Decrement (

15、a-) Negate (-a) Negate 反面，對(duì)立面,25/40,Shift and Rotate Operations,26/40,Logical,Bitwise operations AND, OR, NOT Bitwise 按位,27/40,Conversion,E.g. Binary to Decimal,28/40,Input/Output,May be specific instructions May be done using data movement instructions (memory mapped) May be done by a separate cont

16、roller (DMA),29/40,Systems Control,Privileged instructions CPU needs to be in specific state Ring 0 on 80386+ Kernel mode For operating systems use Privileged 特許的，有特權(quán)的,30/40,Transfer of Control,Branch e.g. branch to x if result is zero Skip e.g. increment and skip if zero ISZ Register1 Branch xxxx A

17、DD A Subroutine call c.f. interrupt call c.f. 請(qǐng)比較,請(qǐng)對(duì)照/參看 (拉丁語(yǔ)）,31/40,Branch Instruction,32/40,Nested Procedure Calls,33/40,Use of Stack,34/40,Stack Frame Growth Using Sample Procedures P and Q,35/40,Exercise For Reader,Find out about instruction set for Pentium and PowerPC Start with Stallings Visit

18、 web sites,36/40,Byte Order(A portion of chips?),What order do we read numbers that occupy more than one byte e.g. (numbers in hex to make it easy to read) 12345678 can be stored in 4x8bit locations as follows,37/40,Byte Order (example),AddressValue (1)Value(2) 1841278 1853456 1865634 1867812 i.e. r

19、ead top down or bottom up? i.e.= that is to say . 這就是說(shuō). 一般性的大辭典上都有解釋，諸如英漢高階,38/40,i.e. 是拉丁文 id est 的縮寫，它的意思就是“那就是說(shuō)，換句話說(shuō)”，等同于“that is，in other words” ，目的是用來(lái)進(jìn)一步解釋前面所說(shuō)的觀點(diǎn)。 e.g. 是拉丁文 exempli gratia 的縮寫，它的意思是“舉個(gè)例子，比如”，等同與“for example”,目的就是用幾個(gè)例子來(lái)說(shuō)明前面的觀點(diǎn)。 etc.是 etcetera 的縮寫，意思是“等等”，相當(dāng)于“and so on” e.g. 和 etc. 不能出現(xiàn)在同一句話中 c.f. 請(qǐng)比較,請(qǐng)對(duì)照/