外文翻譯--單片集成MEMS技術(shù)

Monolithically integrated MEMS technologyIn the past 20 years, CMOS technology has become a major integrated circuit manufacturing technology, manufacturing costs decline at the same time, yield and production has also been greatly improved, COMS technology will continue to increase integration and reduce development of a special size. Today, CMOS integrated process not only be used in the design of integrated circuits, but also to be used in many micro-sensors and micro-actuator, so it can be integrated circuits and micro-sensor integrated with a powerful, intelligent sensors. With micro-sensor constantly expanding the scope of application of the sensor increasingly high demands of the future microsensor the main requirements are: miniaturization and integration of low-power and low-cost high-precision and long life； - and intelligent. Micromachined silicon integrated circuits and the integration of integration, to meet the above-mentioned requirements. At present, the majority of products integrated sensor using hybrid integrated, monolithic integration of a very small percentage. And the realization of single-chip integration is the key to achieving intelligent sensors, in particular monolithic integrated MEMS sensor technology is todays system-on-chip can achieve one of the key technologies. Clearly, monolithic integration of the various technical difficulties analysis of MEMS and have already given the various monolithic integration of MEMS technology is essential.1. Monolithic integration of MEMS technology advantages and the challenges facing。MEMS and CMOS achieve working together, the separate manufacturing CMOS MEMS sensors and integrated circuits, and then cut from their chips, fixed in a common substrate, and, bonded connection, thereby bringing the two integration, This is the so-called mixed (hybrid) method. This method does not produce MEMS manufacturing process for CMOS circuits pollution At the same time, both the production process Noninterference. However, due to signal bonding point and fuses, resulting in high-frequency applications, decline in the quality of signal transmission, and to develop two production lines to increase the cost of the product. In order to address some performance issues, and lower manufacturing costs, and proposed to do in the part of MEMS and CMOS circuits with a substrate, which is produced compatible with CMOS technology or monolithic integrated MEMS technology called CMOS-MEMS technology. This method relative hybrid method generally have the following advantages: First, the performance can be greatly improved, because parasitic capacitance and crosstalk phenomenon can be significantly reduced； second, hybrid method requires sophisticated technology to reduce packaging Sensor Interface affected, and monolithic integration requires packaging technology is relatively simple and therefore, lower cost sensors； third, monolithic integrated sensor array sensor technology is the need to overcome the array sensor and external decoding circuit an effective interconnect bottleneck； Fourth, the development of monolithic integrated mixed development of MEMS products than MEMS products for a short time, and to develop low cost.Monolithic integration of MEMS technology under some of MEMS devices and CMOS circuit can be divided into different order processing before CMOS (pre-CMOS), mixed CMOS (intermediate-CMOS), and after the CMOS (post-CMOS) integrated approach.Post-CMOS approach is in the processing of silicon CMOS circuits End, through some additional MEMS micro-processing technology to achieve monolithic integrated MEMS system, at present, monolithic integration of MEMS technology in this way mainly based. Post-CMOS approach is the main issue on MEMS processing temperature CMOS circuit performance in front of an impact on more serious is that the technology behind high-temperature MEMS processing temperature and metal CMOS process ahead of incompatibility. In the present study as the most polysilicon layer structure of the MEMS example, the densification of phosphorus glass annealing temperature is 950 due to a structural polysilicon layer of stress annealing temperature reached 1050 , which will enable CMOS devices junction depth migration occurred. In particular 800 shallow junction devices junction depth migration will affect device performance. On the other hand, the conventional aluminum metallization process, when the temperature reaches 400-450 , the reliability of CMOS circuits will be severely affected. From the above we can see that: how to overcome behind high-temperature MEMS processing temperature on the micro-structure of the front end processing has been the impact of CMOS circuits integrated MEMS single-chip solution is key to the system. At present, the international community is essential to resolve this issue through three ways: First is the interconnection of refractory metals instead of aluminum metal interconnect, for example, the University of Berkeley to replace tungsten aluminum metal interconnect programmes, such follow-up increased tolerance MEMS processing for high temperature； The second is produced by finding low temperature mechanical properties and excellent substitute materials as structural polysilicon layer； third way is to use its existing structure CMOS MEMS layer as a layer structure.Pre-CMOS integrated approach is to create structure MEMS manufacturing CMOS circuits, although this integrated CMOS technology to overcome post-CMOS method of high-temperature MEMS Technology on CMOS circuits affected, but because of the existence of micro-vertical structure, and therefore, there sensor and circuit interconnection level coverage, but also in the process of CMOS circuits on the micro-structure protection is also a need to consider the issue. Even fine-tune the optimization of CMOS process, such as: gate oxide may be heavily doped layer impact of the structure. In addition, the MEMS technology can not process any of the metal or other materials, such as piezoelectric polymers, and so on, makes this method only suitable for some special applications.Intermediate-CMOS circuits in the CMOS production process to insert some MEMS micro-processing technology to achieve monolithic integrated MEMS approach. This approach has been very mature and have a lot of commercialization of products, is the first study of a single-chip integration method is to solve the pre - and post-CMOS CMOS method effective method problems, but due to the need for the existing standard CMOS or larger BiCMOS process changes, therefore, the use of this method is limited.2.The main monolithic integrated MEMS technology statusAt present, the monolithic integration of MEMS technology mainly to post-CMOS technologies, through a series of compatible with CMOS process on the surface micro-machining and processing to achieve monolithic integration of MEMS. Can be divided into two kinds: one is in the top layer CMOS structure to a structure layer deposition micro-machining； the other is directly CMOS layer structure as the original structure of the MEMS micro-machined.2.1 Deposition of new structural materials for the structure of integrated MEMS technology2.1.1 Polysilicon layer structure as the surface micro-machining technology integrationThis process is typical of modules developed at the University of Berkeley Integrated CMOS and MEMS Technology (modular integration of CMOS with micro-structures, MICS), this method is for the micro-structural polysilicon layer, phosphorus silicon glass (PSG) as a sacrificial layer The surface micro-machining technology. A refractory metal tungsten metal interconnect instead of aluminum metal interconnect to bear behind the polysilicon production needs of micro-structure of high-temperature, but at 600 , tungsten and silicon form easily response by the University of Berkeley in the Contacts release a TiN barrier layer to address this problem. MICS process is the basic process: the completion of tungsten metal CMOS process, the deposition of 300 10-10nm low-temperature oxide (LTO), and then, low pressure chemical vapor deposition 200 10-10nm protection of the silicon nitride film has been produced CMOS circuits, micro-structure and corrosion End CMOS circuit contact hole, No. 1 layer deposition scene doped polysilicon (350 10-10), as CMOS circuits and micro-structure of interconnection lines, in the above deposition to a um PSG thick as a sacrificial layer thickness and deposition of 2 um polysilicon layer structure. No. 2 through another layer polysilicon deposition of a layer of 0.5 um PSG, as well as nitrogen environment in the 1000 rapid thermal annealing for 1 min as a structure to reduce stress polysilicon layer. Finally, the structure of graphics and polysilicon etching out its corrosion layer below the sacrifices (PSG) for the release of micro-structure.2.1.2 Other materials for the structure of the surface micro-machining technology integrationPolycrystalline silicon germanium polysilicon not only with the excellent mechanical properties similar, and, low temperature deposition compatible with the CMOS process, therefore, is being extensively studied. Developed at the University of Berkeley-based structural layer of silicon germanium technology and MICS technology similar. Major technological innovations: First, the protective layer using different materials, before 835 MICS process is the LPCVD silicon nitride, and now it is using a two-tier LTO and intermediate folder is not a stereotypical silicon (a-Si) as a CMOS circuit protective layer, in which the two-step deposition of a-Si, the first step in the deposition 450 ； step deposition in the 410 , this will not damage the temperature of aluminum metal CMOS circuit； Second, the low amylin plot structure as a temperature polysilicon layer of germanium materials, the low pressure chemical vapor deposition (LPCVD) temperature only 400 using rapid thermal annealing temperature of only 5.5 for 30 s. MICS and the temperature polysilicon deposition of more than 600 . From the above two points, we can see that the whole follow-up MEMS processing temperature does not exceed 450 , therefore, not of aluminum metal interconnect CMOS circuits have greatly affected.Aluminum used as a structural material will be a great success, the most successful is the Texas Instruments developed cryogenic surface micro-machining technology, and use this technology successfully produced digital micromirror device (DMD). Technical innovation in the use of sputtering performance as aluminum structural material, and using photoresist as a sacrificial layer, which makes low-temperature post-processing production has been below the SRAM cells were not damaged.Lead zirconate titanate (PZT) of the material has an excellent result piezoelectric properties, pyroelectric properties of ferroelectric properties and dielectric properties and is widely used in ferroelectric memory, as well as high-dielectric materials. At the same time, we can also use lead zirconate titanate piezoelectric effect produced micro-sensors and micro-actuators. PZT thin film silicon technology and integration technology compatible, such as the present based on the metal-organic chemical vapor deposition (OCVD) Methods PZT thin films temperature has been reduced to 430 to 75 , the temperature is lower, therefore, use of such materials as structural layer is a very hopeful and CMOS process integration.2.2 CMOS structure to the original layer to the structure of integrated MEMS technology2.2.1 Sacrifice aluminum micro-machining technologyIf CMOS metal compounds used for the expense of materials, there may be fully compatible with CMOS technology and surface micro-machining small art, this method is called sacrifice aluminum etching (sacrificial aluminum etching, SALE). In many CMOS process, use two layers of aluminum alloy by a metal layer. No. 1 as a sacrificial layer of metal was removed, can create metal dielectric compounds； Layer 2 and passivation of the metal component, 2-layer metal between two dielectric between appropriate structure, they could serve as a mirror electrodes, heat or electric resistance regulator. The basic process include: (1) the protection of electrical contacts are not connected etching (2) corrosion sacrifice aluminum layer； (3) removal rinsed Boundary structure inside the etching agent； (4)-drying bodies.2.2.2 Monocrystal silicon etching and metal activation method.Monomer silicon etching and metal activation method (single crystal reactiveetching and metallization, SCREAM) can be used for manufacturing, beam, the bridge structure, and even silicon can be used to create more complex structures. This approach starts at the End manufacture silicon CMOS circuits, first of all, a layer of coverage deposition contact hole silicon oxide, oxide layer to protect it from the back of CMOS circuits affected, and through reactive ion etching (RIE) of this graphics Oxide layer shielding layer； then RIE etching silicon trench, the depth of up to 10 um, silicon oxide thin film deposition down, and the level of coverage in the side surface. By reactive ion etching of the oxide surface level off due to a vertical surface to be protected, the second reactive ion etching silicon； Finally, the isotropic etch silicon, the release of the microstructure of a suspension, at the same time, etching contact hole oxides, and Sputtering metal, this layer of metal deposition to the aspect ratio of the beam into a capacitive elements with thick resist masking agent for the graphics mode of metal layers. As each step of SCREAM are below 300 under the temperature and, therefore, is compatible with CMOS circuits.2.2.3 Large aspect ratio of CMOS-MEMS TechnologyGamegle Melloa University and the development of CMOS-compatible dry etching method, which isotropic silicon etch applications have insulation film, CMOS dielectric and metal layers in this process, not only for the metal interconnect, but also as a micro-mechanical structure tail. Basic process: First, the standard CMOS process using three-metal process to achieve 0.5 upmN Well, secondly, metal layers 1 and 2 were used as electrical activity layer, and layer 3 as a micro-machining etching mask. Application of the compound CHF3/O2 reactive ion etching (RIE), the entire chip passivation layer to be removed, in the three-tier regional disconnect metal, CMOS laminated film has been etched to the basement, and above covered with Layer 3 CMOS metal thin film laminated retained intact； Finally, the use of SP6/O2 plasma etching in the micro-structural wall not under isotropic etch silicon substrate. Narrow insulating layer and conductive layer fused to create beams and bridges, such as: Comb drive the micro-structure.2.2.4 Processing CMOS-MEMS TechnologyMainly through the etching of silicon substrates, such as processing technology to form the necessary MEMS structure, the technology mainly to the University of Zurich-based. Can be viewed in a positive etching silicon substrate, but also from negative etching silicon substrate, using anisotropic etching (100) in the direction of the characteristics of the silicon etching could be positive not closed micro-structure, such as beams and support film , the choice of etching can be tetramethyl ammonium hydroxide solution (TMATH) or ethylene diamine solution (EDP). From what has been done through the back of the silicon wafer of silicon can be pitting the closure of the dielectric film, the need for a definition of additional patch mask the size of the commonly used candle is engraved on KOH. XeF2 dry etching using the post-CMOS technology has also made great development. XeP2 is an anisotropic etching of silicon, etching at high velocity, it is an inert gas xenon rare compounds. XeP2 neither IC insulating layer etching, etching aluminum or metal compounds, therefore, and CMOS compatible. After the appropriate regional design, connectivity and processing mask, opened in designated parts insulating layer, so that local exposure to silicon substrate etching agent. XeF2 because that is not etched ceramic, not plastic etching and thus suitable for CMOS integrated micro-processing system. In the use of this method can be completed with CMOS chip micro-etching mask institutions.3.Development Trend Monolithically integrated MEMS technology has been developing for more than 10 years, has been the rapid development has also seen the emergence of a MEMS manufacturing services organizations and enterprises, which will be some special organizations or directly from the IC manufacturers to provide MEMS processing. IC Microsystems representative of the direction of technology development organizations, including the United States and Europe TIMACMP MOSIS.Europractice； North Kaluona state Croons Integrated Microsystems Inc., in addition to providing the basic CMOS process, the body also provides micro-machining and surface emblem processing, LIGA process, as well as multi-user MEMS technology； the United States Sandia National Laboratory development of the multi-storey hyperplane polysilicon technology has been commercialized in Europe in the application-specific integrated circuit manufacturing technology research, including Austria Microsystems and Switzerlands EM Microelectronics. There are many special silicon-based sensor technology has also been finding out, for example, Germanys Luobaitebo Oxfam and the Norwegian SensoNor companies. Judging from the current situation, integrated MEMS technology will have the following trends: (1) post-CMOS integrated approach will continue to be the main future development of technology, and the existing laboratories have developed various post-CMOS single-chip integrated MEMS technology industry； (2) in the integrated MEMS system more complex integrated circuit including digital interfaces and microcontrollers, so that a more powerful, cheaper intelligent systems； (3) the development of CMOS chip packaging technology protection against environmental impacts, not only need to develop a system to integrate the MEMS package, but also need to adapt to the development of the single-chip package integrated MEMS technology.4.Concluding remarks Monolithic Integrated Intelligent MEMS sensor is the key to the development of IC industry is an important direction. Although various methods are some problems still exist, however, with its constant research and CMOS process compatibility problems will be all the solutions. In this paper, monolithic integration of MEMS technology to the requirements were discussed, and monolithic integration of various characteristics of MEMS technology, a process, at the same time, also gives future monolithic integration of MEMS technology development trend of the future.單片集成MEMS技術(shù)在過去的20年中，CMOS技術(shù)已成為集成電路主要制造工藝，制造成本下降的同時，成品率和產(chǎn)量也得到很大提高，COMS工藝將繼續(xù)以增加集成度和減小特制尺寸向前發(fā)展。當(dāng)今，CMOS集成工藝不僅被利用在集成電路設(shè)計上，而且，也被利用在很多微傳感器和微執(zhí)行器上，這樣可以把微傳感器與集成電路集成在一起，構(gòu)成功能強大的智能傳感器。隨著微傳感應(yīng)用范圍的不斷擴大，對傳感器的要求也越來越高，對未來微傳感器的主要要求是：微型化和集成化；低功耗和低成本；高精度和長壽命；多功能和智能化。硅微機械和集成電路的一體化集成可以滿足上述要求。目前，集成傳感器的產(chǎn)品多 用 集成，單片集成的 很小。而 單片集成是 傳感器智能化的 ，特 是單片集成MEMS傳感器技術(shù)也是當(dāng)今片上 片能 的 技術(shù)一?？?，對 單片集成MEMS技術(shù) 行 以 目前已的 單片集成MEMS技術(shù)是 要的。單片集成MEMS技術(shù)的和的MEMS和CMOS同工currency1是 制造MEMS傳感器和CMOS集成電路，“， 的片fifl， 在一同的上， 且， ，這樣 ”的集成，這是的 。這 不產(chǎn)MEMS制造過 對CMOS電路的，同時，”產(chǎn)過 不。是， 過 和 ， 在高 應(yīng)用時， 傳 量下降， 且，fl發(fā) 產(chǎn)增加 產(chǎn)品的成本。為一 能 ， 降低制造成本，提 把MEMS 在和CMOS電路同一 上，也是產(chǎn) 與CMOS工藝 單片集成MEMS技術(shù)CMOSMEMS技術(shù)。這 對 的來 下：一， 能能得到很大的提高， 為電 和 可以 減小； ， 要的技術(shù)以減小傳感器 的 ，而單片集成 要的技術(shù)對簡單，以，降低傳感器成本；三，單片集成傳感器技術(shù)也是陣列傳感器的 要，是克服陣列傳感器與外圍譯碼電路 瓶頸的一 效； 四，fl發(fā)單片集成MEMS產(chǎn)品 fl發(fā) MEMS產(chǎn)品 的時間短，而且，fl發(fā)成本低。單片集成MEMS技術(shù)根據(jù)MEMS器件 與CMOS電路 加工順序不同可以 為前CMOSpeCMOS、 CMOSntemeateCMOS“CMOSpostCMOS集成。postCMOS是在加工完CMOS電路的硅片上，通過一 附加MEMS微細(xì)加工技術(shù)以 單片集成MEMS ，目前，單片集成MEMS技術(shù)主要以這 為主。postCMOS主要 是MEMS加工工藝溫度對前的CMOS電路 能產(chǎn) ，更為嚴(yán)重的是“高溫MEMS加工工藝溫度與前CMOS工藝金屬化不 。以目前研究最多的多硅currency1為結(jié)構(gòu)層的MEMS為 ，使磷硅玻璃 密化退火溫度為950，而使currency1為結(jié)構(gòu)層多硅的應(yīng)力退火溫度則達(dá)到 050，這將使CMOS器件結(jié)深發(fā)遷移。特 是800時淺結(jié)器件的結(jié)深遷移 器件的 能。另一， 用 規(guī)鋁金屬化工藝時，當(dāng)溫度達(dá)到400450時，CMOS電路可靠 將受到嚴(yán)重的 。以上可以看 ： 何克服“高溫MEMS微結(jié)構(gòu)加工溫度對前的已加工完的CMOS電路 是 單片集成MEMS 在。目前，國際上 這 基本是通過3式： 一 是以 熔金屬化 代替鋁金屬化 ， ，伯克利大學(xué)的以鎢代替鋁金屬 案，這樣提高 忍“續(xù)加工MEMS 的高溫； 式是通過尋找低制currency1溫度且機械 能良的材料代替多硅currency1為結(jié)構(gòu)層材料； 三 式是利用CMOS本身已 結(jié)構(gòu)層currency1為MEMS結(jié)構(gòu)層。peCMOS集成是先制造MEMS結(jié)構(gòu)“制造CMOS電路，這 集成CMOS技術(shù)雖克服postCMOS中MEMS高溫工藝對CMOS電路的， 存在垂直的微結(jié)構(gòu)，以，存在傳感器與電路 臺階覆蓋 ，而且，在CMOS電路工藝過 中對微結(jié)構(gòu)的保護也是一要考慮的 。甚至已化微調(diào)的CMOS工藝流 ， ：柵氧化可能被重?fù)降慕Y(jié)構(gòu)層 。另外，MEMS工藝過 中不能 任何的金屬其他的材料， 壓電材料聚 物等，使得這 只適 一 特殊應(yīng)用。ntemeateCMOS是在CMOS電路產(chǎn)過 中插入一 MEMS微細(xì)加工工藝來 單片集成MEMS的。這 已很成熟， 已 很多商品化產(chǎn)品，也是研究最早一 單片集成，是 peCMOS和postCMOS存在 效，是， 要對 的標(biāo)準(zhǔn)CMOSBCMOS工藝 行較大的 ， ，這 的使用 一 制。2 單片集成MEMS的主要技術(shù) 目前，單片集成MEMS技術(shù)主要以postCMOS技術(shù)為主，通過一 列的與CMOS工藝 的 微細(xì)加工和體加工 單片集成MEMS。 可 為2 ：一 是在CMOS結(jié)構(gòu)層上 一層結(jié)構(gòu)層的微加工；另一 是直 以CMOS 的結(jié)構(gòu)層currency1為MEMS結(jié)構(gòu)層的微加工。2 的結(jié)構(gòu)材料currency1MEMS結(jié)構(gòu)的集成技術(shù)2 多硅currency1為結(jié)構(gòu)層的集成 微細(xì)加工技術(shù)這 工藝 型代 是伯克利大學(xué)fl發(fā) 集成CMOS與MEMS工藝mo a nte aton o CMOS t m ost t es，M CS，這 是以多硅為微結(jié)構(gòu)層，磷硅玻璃 S currency1為 層的 微細(xì)加工技術(shù)。 用 熔金屬鎢的金屬化 代替鋁金屬化 以 受“的產(chǎn)多硅微結(jié)構(gòu) 要的高溫，是，在 00時，鎢 與硅 成 應(yīng)，伯克利大學(xué)是通過在 上一層層來 這一 的。M CS工藝基本流 是：完成鎢金屬化的CMOS工藝“， 300 0 0nm低溫氧化物O，“，低壓化學(xué)currency1 200 0 0nm的化硅“保護已產(chǎn)的CMOS電路，完微結(jié)構(gòu)與CMOS電路的 “， 層 fi摻多硅350 0 0currency1為CMOS電路與微結(jié)構(gòu)的 ， 在上 mfl的 S currency1為 層以 fl度為2 m多硅結(jié)構(gòu)層。通過在 2層多硅上 一層0 5 m的 S ，以 在currency1 下的 000退火 mn來降低currency1為結(jié)構(gòu)層的多硅應(yīng)力。最“，多硅結(jié)構(gòu) 以 其下的 層 S 以微結(jié)構(gòu)。2 2 以其他材料currency1結(jié)構(gòu)層集成 微細(xì)加工技術(shù)多硅不僅 與多硅的良機械 能，而且， 溫度低與CMOS工藝 ，以，目前被”研究。伯克利大學(xué)fl發(fā)的基 硅結(jié)構(gòu)層的工藝與M CS工藝基本。主要技術(shù) ： 一，保護層 用不同的材料，以前M CS工藝 用835的 C 化硅，而 在則是 用層O和中間一層不型硅aScurrency1為CMOS電路保護層，其中，aS ， 一 在450； 則在4 0，這樣溫度是不鋁金屬化CMOS電路； ， 用低