處理器設(shè)計(jì)全部代碼

1、代碼一頂層模塊module MIPS_C(clk,rst,MIPS_out ); input clk,rst; output 7:0MIPS_out; wire 31:0ALU_DC;wire 31:0Pc_out;wire 5:0op;wire 5:0func;wire ALUSrcA;wire ALUSrcB;/wire Load_Mem;wire MemtoReg;wire RegDst;wire ExtOp;/wire MemWr;wire RegWr;wire 31:0instruct; wire PcWrite;wire 31:0imm32;wire 15:0imm16;wire

2、25:0target;wire 31:0rdata2;wire 31:0rdata1;wire 31:0rdata3;wire ALU_CLK;wire 31:0Mem_Dout;wire 4:0rt;wire 4:0rd;wire 4:0rs;wire 31:0ALU_DB;wire 31:0ALU_DA;wire 31:0wdata;wire 4:0waddr;wire Branch;wire Jump;wire 31:0Mem_Din;wire ALU_OverFlow;wire ALU_ZERO;wire 4:0shamt;wire 4:0ALU_SHIFT;assign MIPS_o

3、ut=rdata37:0;Main_control main_control( .rst(rst), .op(op), .ALUSrcA(ALUSrcA),.ALUSrcB(ALUSrcB),.MemtoReg(MemtoReg),.RegDst(RegDst),.ExtOp(ExtOp), .PcWrite(PcWrite),.RegWr(RegWr),.clk(clk) ); Fetch_top fetch_top(.clk(clk), .rst(rst), .instruct(instruct), .ALU_DA(ALU_DA), .Jump(Jump), .Branch(Branch)

4、, .PcWrite(PcWrite), .ALU_DB(ALU_DB), .Pc_out(Pc_out) ); decode Decode(.instruct(instruct), .op(op), .rs(rs), .rt(rt), .rd(rd), .func(func), .shamt(shamt), .imm16(imm16), .target(target) );regfile Regfile (.clk(clk), .rst(rst), .RegWr(RegWr), .waddr(waddr), .wdata(wdata), .raddr1(rs), .rdata1(rdata1

5、), .raddr2(rt), .rdata2(rdata2) , .rdata3(rdata3) ); /*Memory mem ( .Mem_Adr(Mem_Adr), .MemWr(MemWr), .rst(rst), .clk(clk), .Mem_Din(rdata2), .Mem_Dout(Mem_Dout) );*/ Imm imm( .rst(rst), .imm16(imm16),.ExtOp(ExtOp),.imm32(imm32);flag Flag(.ALU_DA(ALU_DA), .ALU_DB(ALU_DB), .op(op), .func(func), .Jump

6、(Jump), .Branch(Branch) ); ALU_top alu_top ( .ALU_CLK(clk),.rst(rst),.func(func),.op(op),.ALU_DA(ALU_DA),.ALU_DB(ALU_DB),.ALU_SHIFT(shamt),.ALU_ZERO(ALU_ZERO),.ALU_OverFlow(ALU_OverFlow),.ALU_DC(ALU_DC) );data_select DATA_select(.ALUSrcA(ALUSrcA),.ALUSrcB(ALUSrcB),.MemtoReg(MemtoReg),.RegDst(RegDst)

7、,.imm32(imm32),.target(target),.rdata2(rdata2),.rdata1(rdata1),.ALU_DC(ALU_DC),.Mem_Dout(Mem_Dout),.rt(rt),.rd(rd),.ALU_DB(ALU_DB),.ALU_DA(ALU_DA),.wdata(wdata),.waddr(waddr) );endmodule二主控模塊module Main_control(clk,rst,op,ALUSrcA,ALUSrcB,MemtoReg,RegDst,ExtOp, PcWrite,RegWr ); input clk,rst; input 5

8、:0op; output reg ALUSrcA; output reg ALUSrcB; output reg MemtoReg; output reg RegDst; output reg ExtOp; output reg RegWr; output reg PcWrite; reg 3:0state; reg 3:0next_state; parameter State_IR = 4'b0000,/fetch adder State_decode = 4'b0001, /decode State_MemCalc= 4'b0010,/store calculate

9、 adder State_MemRD = 4'b0011 , /read Mem State_MemRDend= 4'b0100 , /read Mem finish State_MemWr = 4'b0101 ,/write MEm State_R = 4'b0110,/Rzhixing State_Rend = 4'b0111,/Rfinish State_B = 4'b1000,/Bzhixing State_J = 4'b1001;/jzhilingalways(posedge clk or posedge rst) begini

10、f(rst) state <= 4'b0000;else state <=next_state; endalways(*) begin case(state)4'b0000: begin next_state<=4'b0001;end4'b0001: beginnext_state3<=(op5)&(op4)&(op3)&op2&(op1)&op0) | (op5)&(op4)&(op3)&(op2)&(op1)&(op0);next_state2<=(

11、op5)&(op4)&(op3)&(op2)&(op1)&(op0);next_state1<=(op5)&(op4)&(op3)&(op2)&(op1)&(op0) |(op5)&(op4)&(op3)&(op2)&(op1)&(op0)|(op5)&(op4)&(op3)&(op2)&(op1)&(op0);next_state0<=(op5&(op4)&op3&(op2)&(op1)&a

12、mp;(op0);end/*4'b0010:beginnext_state<=4'b0011; end*/ 4'b0010:beginnext_state3<=1'b0;next_state2<=op5&(op4)&(op3)&(op2)&op1&op0;next_state1<=(op5)&(op4)&(op3)&(op2)&(op1)&(op0);next_state0<=1'b1; end4'b0011:beginnext_stat

13、e<=4'b0100;end4'b0100:beginnext_state<=4'b0000;end4'b0101:begin next_state<=4'b0000;end4'b0110:beginnext_state<=4'b0111;end4'b0111:beginnext_state<=4'b0000;end4'b1000:begin next_state<=4'b0000;end4'b1001:beginnext_state<=4'b000

14、0;end endcaseendalways(posedge clk)begincase(state)4'b0000: beginALUSrcA<=0;ALUSrcB<=1;/Load_Mem<=0;MemtoReg<=0;RegDst<=0; ExtOp<=1; /MemWr<=0; RegWr<=0; PcWrite<=1; end4'b0001: beginALUSrcA<=0; ALUSrcB<=1;/Load_Mem<=0;MemtoReg<=0;RegDst<=0; ExtOp<

15、;=0; /MemWr<=0; RegWr<=0; PcWrite<=0;end4'b0010: beginALUSrcA<=0;ALUSrcB<=1;/Load_Mem<=1;MemtoReg<=1;RegDst<=0; ExtOp<=1; /MemWr<=0; RegWr<=0; PcWrite<=0; end4'b0011: beginALUSrcA<=0;ALUSrcB<=0;/Load_Mem<=1;MemtoReg<=1;RegDst<=0; ExtOp<=0

16、; /MemWr<=0; RegWr<=0; PcWrite<=0; end 4'b0100: beginALUSrcA<=0;ALUSrcB<=0;/Load_Mem<=0;MemtoReg<=0;RegDst<=0; ExtOp<=0; /MemWr<=0; RegWr<=1; PcWrite<=0; end4'b0101:beginALUSrcA<=0;ALUSrcB<=1;/Load_Mem<=1;MemtoReg<=0;RegDst<=0; ExtOp<=0;

17、/MemWr<=1; RegWr<=1; PcWrite<=0;end 4'b0110: beginALUSrcA<=0;ALUSrcB<=0;/Load_Mem<=0;MemtoReg<=0;RegDst<=1; ExtOp<=0; /MemWr<=0; RegWr<=0; PcWrite<=0; end4'b0111: beginALUSrcA<=0;ALUSrcB<=0;/Load_Mem<=0;MemtoReg<=1;RegDst<=1; ExtOp<=0; /M

18、emWr<=0; RegWr<=1; PcWrite<=0; end4'b1000: beginALUSrcA<=0;ALUSrcB<=1;/Load_Mem<=0;MemtoReg<=0;RegDst<=0; ExtOp<=1; /MemWr<=0; RegWr<=0; PcWrite<=1; end 4'b1001: beginALUSrcA<=1;ALUSrcB<=0;/Load_Mem<=0;MemtoReg<=0;RegDst<=0; ExtOp<=0; /Me

19、mWr<=0; RegWr<=0; PcWrite<=0; end endcase endendmodule三取指模塊（1）頂層module Fetch_top(clk,rst,instruct,ALU_DA,Jump,Branch,PcWrite,ALU_DB,Pc_out ); input clk,rst; input 31:0ALU_DA; input Jump,Branch,PcWrite; input 31:0ALU_DB; output31:0 instruct; output 31:0Pc_out; fetch FETCH(.Pc_out(Pc_out),.in

20、struct(instruct) );pc PC( .rst(rst),.ALU_DA(ALU_DA),.Jump(Jump),.Branch(Branch),.Pc_out(Pc_out),.ALU_DB(ALU_DB),.PcWrite(PcWrite) );endmodule(2)取指module fetch(Pc_out,instruct );input31:0Pc_out;output 31:0instruct;wire 31:0store0:31; assign store32'h00 = 32'b000000_00001_00000_00011_00000_100

21、000;/jia assign store32'h01 = 32'b000000_00001_00000_00011_00000_100000;/jiaassign store32'h02 = 32'b000000_00111_00110_00111_00000_100010; /減一assign store32'h03 = 32'b000101_00111_00000_00000_00000_000001;/不等跳轉(zhuǎn)assign store32'h04 = 32'b000000_00011_00100_00011_00000_1

22、00000;/jiaassign store32'h05 = 32'b000000_01000_00110_00111_00000_100010; /減一assign store32'h06 = 32'b000101_00111_00000_00000_00000_000001;/不等跳轉(zhuǎn)assign store32'h07 = 32'b000000_00101_00010_00011_00000_100000;/jiaassign store32'h08 = 32'b000000_00111_00110_00111_00000_

23、100010; /減一assign store32'h09 = 32'b000101_00111_00000_00000_00000_000001;/不等跳轉(zhuǎn)assign store32'hA = 32'b000000_00011_00010_00011_00000_100101; / huofeiassign store32'h0B = 32'b000000_01000_00110_00111_00000_100010; /減一assign store32'h0C = 32'b000101_00111_00000_00000_0

24、0000_000001;/不等跳轉(zhuǎn)assign store32'h0D = 32'b101000_00000_00000_00000_00000_000000;/ assign instruct = storePc_out;endmodule（3）程序計(jì)數(shù)器module pc(rst,Jump,Branch,Pc_out,ALU_DA,PcWrite,ALU_DB );input 31:0ALU_DA;input 31:0ALU_DB;input Jump,Branch,rst,PcWrite;output reg 31:0Pc_out;always(posedge PcWri

25、te)beginif(rst)Pc_out<=32'h00; else if(PcWrite) begin if (Jump) Pc_out<=ALU_DA; else if (Branch) Pc_out<=Pc_out-ALU_DB;else Pc_out<=Pc_out+1; end else Pc_out<=Pc_out;end endmodule四譯碼模塊module decode(instruct,op,rs,rt,rd,func,shamt,imm16,target); input 31:0instruct; output reg 5:0op

26、; output reg4:0rs,rt,rd; output reg4:0shamt; output reg5:0func; output reg15:0imm16; output reg 25:0target; always(*) begin op5:0=instruct31:26; rs4:0=instruct25:21; rt4:0=instruct20:16; rd4:0=instruct15:11; shamt4:0=instruct10:6; func5:0=instruct5:0; imm1615:0=instruct15:0; target25:0=instruct25:0;

27、 end endmodule 五寄存器模塊module regfile( inputclk,input rst,input RegWr, input4:0waddr, input31:0wdata, input4:0raddr1,output31:0 rdata1, input4:0raddr2, output31:0 rdata2,output31:0 rdata3);reg31:0 regs0:8;/Write operationalways (posedge clk or posedge rst) begin if(rst) begin regs0<=32'b0; regs

28、1<=32'b00000000_00000000_00000000_00001100; regs2<=32'b00000000_00000000_00000000_00000000; regs3<=32'b0; regs4<=32'b00000000_00000000_00000000_11000000; regs5<=32'b00000000_00000000_00000000_11100111; /regs6<=32'b00000000_00000000_00000000_00000010; regs6&l

29、t;=32'b00000000_01011111_01111000_01000000;/0.5/regs7<=32'b00000000_00000000_00000000_00000001; regs7<=32'b00000010_11111010_11110000_10000000;/1 /regs8<=32'b00000000_00000000_00000000_00000011; regs8<=32'b00011111_01001010_11011101_01000000;/10.5 end else beginif(Reg

30、Wr= 1'b1) && (waddr != 5'h0) begin regswaddr <= wdata; end endend/Read port1 operation assign rdata1 = (raddr1 = 5'd0) ? 32'd0 : regsraddr1;/Read port2 operation assign rdata2 = (raddr2 = 5'd0) ? 32'd0 : regsraddr2; assign rdata3 = regs3;endmodule 六立即數(shù)擴(kuò)展塊module Imm

31、(rst,imm16,ExtOp,imm32); input rst; input ExtOp; input 15:0imm16; output 31:0imm32; reg31:0 bus1; always(*) if(rst) bus1<=32'b0; else if(imm1615=0) begin bus131:16<=16'b0000_0000_0000_0000; bus115:0<=imm1615:0; end else if(imm1615=1) begin bus131:16<=16'b1111_1111_1111_1111;

32、bus115:0<=imm1615:0; end assign imm32 = (ExtOp=1)?bus1:imm32; endmodule七部分控制信號(hào)產(chǎn)生塊module flag(ALU_DA,ALU_DB,op,func,Jump,Branch); input 31:0ALU_DB; input 31:0ALU_DA; input 5:0op; input 5:0func; output reg Jump; output reg Branch; always(*) begin if(op=6'b101000) Jump<=1; else Jump<=0; en

33、d always(*) case(op) 6'b000100: begin if(ALU_DA=ALU_DB) Branch<=1; else Branch<=0; end 6'b000101: begin if(ALU_DA=ALU_DB) Branch<=0; else Branch<=1; end default Branch<=0;endcase endmodule八邏輯運(yùn)算模塊（1）頂層模塊module ALU_top(ALU_CLK,rst,func,op,ALU_DA,ALU_DB,ALU_SHIFT,ALU_ZERO,ALU_Ove

34、rFlow,ALU_DC );input ALU_CLK;input rst;input 5:0func;input5:0op;input 31:0ALU_DA;input 31:0ALU_DB;input 4:0ALU_SHIFT;output ALU_ZERO;output ALU_OverFlow;output 31:0 ALU_DC;wire3:0 ALU_ctr;wire 3:0alu_clt; ALU_control alu_control( .ALU_CLK(ALU_CLK),.rst(rst),.func(func),.op(op),.ALU_ctr(ALU_ctr);ALU

35、alu (.ALU_DA(ALU_DA), .ALU_DB(ALU_DB),.alu_clt(ALU_ctr),.alu_shift(ALU_SHIFT),.ALU_Zero(ALU_ZERO),.Alu_Overflow(ALU_OverFlow),.ALU_Dout(ALU_DC);endmodule(2)運(yùn)算控制塊module ALU_control( ALU_CLK,rst,func,op,ALU_ctr); input rst,ALU_CLK; input 5:0op; input 5:0func; output reg3:0ALU_ctr; reg 3:0ins; always(*

36、) if(op=6'b0) case(func) 6'b000010:ins3:0<=4'b0000; 6'b100000:ins3:0<=4'b0001; 6'b000111:ins3:0<=4'b0010; 6'b100101:ins3:0<=4'b0011; 6'b000100:ins3:0<=4'b0100; 6'b000001:ins3:0<=4'b0101; 6'b000110:ins3:0<=4'b0110; 6'

37、;b001000:ins3:0<=4'b0111; 6'b001001:ins3:0<=4'b1111; 6'b000101:ins3:0<=4'b1101; 6'b001010:ins3:0<=4'b1110; endcase else case(op) 6'b001000:ins3:0<=4'b0001; 6'b001001:ins3:0<=4'b0000; 6'b001100:ins3:0<=4'b0101; 6'b001101:ins

38、3:0<=4'b0100; 6'b100011:ins3:0<=4'b0001; 6'b101011:ins3:0<=4'b0001; 6'b001010:ins3:0<=4'b0111; 6'b001011:ins3:0<=4'b0110; 6'b000100:ins3:0<=4'b0100; 6'b000101:ins3:0<=4'b0100; endcasealways(posedge ALU_CLK) if(rst) ALU_ctr<=

39、4'b0; else ALU_ctr3:0<=ins3:0; endmodule (3)運(yùn)算模塊module ALU(ALU_DA,ALU_DB,alu_clt,alu_shift,ALU_Zero,Alu_Overflow,ALU_Dout);input 31:0 ALU_DA;input 31:0 ALU_DB;input 3:0 alu_clt;input 4:0 alu_shift;output ALU_Zero;output Alu_Overflow;output 31:0 ALU_Dout;reg 31:0 ALU_Dout;wire 1:0 OPctr;wire S

40、UBctr;wire ANDctr;wire OVctr;wire SIGctr;reg 31:0 SLL_M,SRL_M,SRA_M;assign SUBctr = alu_clt2;assign ANDctr = alu_clt0;assign OVctr = !alu_clt1&alu_clt0;assign SIGctr = alu_clt0;assign OPctr1 = alu_clt2&alu_clt1|alu_clt3;assign OPctr0 = alu_clt1;always(*)begin case(alu_shift) 5'b00000:SRL

41、_M31:0=ALU_DB31:0; 5'b00001:SRL_M31:0=1'b0,ALU_DB31:1; 5'b00010:SRL_M31:0=2'b0,ALU_DB31:2; 5'b00011:SRL_M31:0=3'b0,ALU_DB31:3; 5'b00100:SRL_M31:0=4'b0,ALU_DB31:4; 5'b00101:SRL_M31:0=5'b0,ALU_DB31:5; 5'b00110:SRL_M31:0=6'b0,ALU_DB31:6; 5'b00111:SRL_

42、M31:0=7'b0,ALU_DB31:7; 5'b01000:SRL_M31:0=8'b0,ALU_DB31:8; 5'b01001:SRL_M31:0=9'b0,ALU_DB31:9; 5'b01010:SRL_M31:0=10'b0,ALU_DB31:10; 5'b01011:SRL_M31:0=11'b0,ALU_DB31:11; 5'b01100:SRL_M31:0=12'b0,ALU_DB31:12; 5'b01101:SRL_M31:0=13'b0,ALU_DB31:13; 5

43、'b01110:SRL_M31:0=14'b0,ALU_DB31:14; 5'b01111:SRL_M31:0=15'b0,ALU_DB31:15; 5'b10000:SRL_M31:0=16'b0,ALU_DB31:16; 5'b10001:SRL_M31:0=17'b0,ALU_DB31:17; 5'b10010:SRL_M31:0=18'b0,ALU_DB31:18; 5'b10011:SRL_M31:0=19'b0,ALU_DB31:19; 5'b10100:SRL_M31:0=20

44、'b0,ALU_DB31:20; 5'b10101:SRL_M31:0=21'b0,ALU_DB31:21; 5'b10110:SRL_M31:0=22'b0,ALU_DB31:22; 5'b10111:SRL_M31:0=23'b0,ALU_DB31:23; 5'b11000:SRL_M31:0=24'b0,ALU_DB31:24; 5'b11001:SRL_M31:0=25'b0,ALU_DB31:25; 5'b11010:SRL_M31:0=26'b0,ALU_DB31:26; 5&#

45、39;b11011:SRL_M31:0=27'b0,ALU_DB31:27; 5'b11100:SRL_M31:0=28'b0,ALU_DB31:28; 5'b11101:SRL_M31:0=29'b0,ALU_DB31:29; 5'b11110:SRL_M31:0=30'b0,ALU_DB31:30; 5'b11111:SRL_M31:0=31'b0,ALU_DB31; default: SRL_M31:0=ALU_DB31:0; endcaseendalways(*)begin case(alu_shift) 5

46、9;b00000:SLL_M31:0=ALU_DB31:0; 5'b00001:SLL_M31:0=ALU_DB30:0,1'b0; 5'b00010:SLL_M31:0=ALU_DB29:0,2'b0; 5'b00011:SLL_M31:0=ALU_DB31:3,3'b0; 5'b00100:SLL_M31:0=ALU_DB31:4,4'b0; 5'b00101:SLL_M31:0=ALU_DB31:5,5'b0; 5'b00110:SLL_M31:0=ALU_DB31:6,6'b0; 5'

47、;b00111:SLL_M31:0=ALU_DB31:7,7'b0; 5'b01000:SLL_M31:0=ALU_DB31:8,8'b0; 5'b01001:SLL_M31:0=ALU_DB31:9,9'b0; 5'b01010:SLL_M31:0=ALU_DB31:10,10'b0; 5'b01011:SLL_M31:0=ALU_DB31:11,11'b0; 5'b01100:SLL_M31:0=ALU_DB31:12,12'b0; 5'b01101:SLL_M31:0=ALU_DB31:13,13'b0; 5'b01110:SLL_M31:0=ALU_DB31:14,14'b0; 5'b01111:SLL_M31:0=ALU_DB31:15,15'b0; 5'b10000:SLL_M31:0=ALU_DB31:16,16'b0; 5'b10001:SLL_M31:0=ALU_DB31:17,17'b0; 5'b10010:SLL_M31: