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1、/* hw_pll.c* Created on: 2012-4-17* Author: lenovo*/總線頻率設(shè)置：64#i nclude"com mon .h"#i nclude "hw_pll.h"/鎖相環(huán)頻率為50/12*54=225M測(cè)試函數(shù)void pllinit225M (void )uin t32_t temp_reg;/使能IO端口時(shí)鐘SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK| SIM_SCGC5_PORTB_MASK| SIM_SCGC5_PORTC_MASK| SIM_SCGC5_PORTD_MASK|

2、SIM_SCGC5_PORTE_MASK );/這里處在默認(rèn)的FEI模式/首先移動(dòng)到FBE模式MCG_C2 = 0;MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HG0_MASK | MCG_C2_EREFS_MASK;/初始化晶振后釋放鎖定狀態(tài)的振蕩器和GPIOSIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;LLWU_CS |= LLWU_CS_ACKISO_MASK;/選擇外部晶振，參考分頻器，清IREFS來啟動(dòng)外部晶振011 If RANGE = 0, Divide Factor is 8; for all other RANGE values,

3、Divide Factor is256.MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);/等待晶振穩(wěn)定/while (!(MCG_S & MCG_S_OSCINIT_MASK)/ 等待鎖相環(huán)初始化結(jié)束while (MCG_S & MCG_S_IREFST_MASK)/ 等待時(shí)鐘切換到外部參考時(shí)鐘while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2)/進(jìn)入FBE模式，0x18=25 分頻=2M,0x08=15 分頻=3.333M0x09=16 分頻=3.1

4、25M,0x10=17 分頻=2.94M0x11=18 分頻=2.7778M0x12=19 分頻=2.63M,0x13=20 分頻=2.5MMCG_C5 = MCG_C5_PRDIV(0x0b);/確保MCG_C6處于復(fù)位狀態(tài)，禁止 LOLIE、PLL、和時(shí)鐘控制器，清 PLL VCO分頻器MCG_C6 = 0x0;/保存FMC_PFAPR當(dāng)前的值temp_reg = FMC_PFAPR;/通過M&PFD 置位MOPFD來禁止預(yù)取功能FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK |FMC_PFAPR_M5PFD_MAS

5、K| FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK |FMC_PFAPR_M2PFD_MASK| FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;/設(shè)置系統(tǒng)分頻器/MCG=PLL, core = MCG, bus = MCG/3, FlexBus = MCG/3, Flash clock= MCG/9SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2)| SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(

6、8);/從新存FMC_PFAPR的原始值FMC_PFAPR = temp_reg;/ 設(shè)置 VCO 分頻器，使能 PLL為 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30);/VDIV = 31 (x54)/VDIV = 26 (x50)while (!(MCG_S & MCG_S_PLLST_MASK);/ wait for PLL status bit to setwhile (!(MCG_S & MCG_S_LOCK_MASK);/ Wait for LOC

7、K bit to set/進(jìn)入PBE模式/通過清零CLKS位來進(jìn)入PEE模式/ CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=OMCG_C1 &=MCG_C1_CLKS_MASK;/等待時(shí)鐘狀態(tài)位更新while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3); SIM_CLKDIV2 |= SIM_CLKDIV2_USBDIV(1);/設(shè)置跟蹤時(shí)鐘為內(nèi)核時(shí)鐘SIM_SOPT2 |= SIM_SOPT2_TRACECLKSEL_MASK;/在PTA6引腳上使

8、能 TRACE_CLKOU功能PORTA_PCR6 = ( PORT_PCR_MUX(Ox7);/使能FlexBus模塊時(shí)鐘SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;/在PTA6引腳上使能FB_CLKOUT功能PORTC_PCR3 = ( PORT_PCR_MUX(0x5);/鎖相環(huán)頻率為 50/13*55=211.538462M測(cè)試函數(shù)void pllinit211M(void )256.uin t32_t temp_reg;/使能IO端口時(shí)鐘SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK| SIM_SCGC5_PORTB_MASK| SI

9、M_SCGC5_PORTC_MASK| SIM_SCGC5_PORTD_MASK| SIM_SCGC5_PORTE_MASK );/這里處在默認(rèn)的FEI模式/首先移動(dòng)到FBE模式MCG_C2 = 0;/MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG,/初始化晶振后釋放鎖定狀態(tài)的振蕩器和GPIOSIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;LLWU_CS |= LLWU_CS_ACKISO_MASK;/選擇外部晶振，參考分頻器，清IREFS來啟動(dòng)外部晶振/011 If RANGE = 0, Divide Factor is 8

10、; for all other RANGE values,MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);/等待晶振穩(wěn)定/while (!(MCG_S & MCG_S_OSCINIT_MASK)C2_EREFS_MASK;Divide Factor is/等待鎖相環(huán)初始化結(jié)/等待時(shí)鐘切換到外部參while (MCG_S & MCG_S_IREFST_MASK)考時(shí)鐘while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2)/進(jìn)入FBE模式，0x18=25 分

11、頻=2M,0x08=15 分頻=3.333M0x09=16 分頻=3.125M,0x10=17 分頻=2.94M/0x11=18 分頻=2.7778M/0x12=19 分頻=2.63M,/0x13=20 分頻=2.5MMCG_C5 = MCG_C5_PRDIV(0x0C);/確保MCG_C6處于復(fù)位狀態(tài)，禁止 LOLIE、PLL、和時(shí)鐘控制器，清 PLL VCO分頻器MCG_C6 = 0x0;/保存FMC_PFAPR當(dāng)前的值temp_reg = FMC_PFAPR;/通過M&PFD 置位M0PFD來禁止預(yù)取功能FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FM

12、C_PFAPR_M6PFD_MASK |FMC_PFAPR_M5PFD_MASK| FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK |FMC_PFAPR_M2PFD_MASK| FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;/設(shè)置系統(tǒng)分頻器MCG=PLL, core = MCG, bus = MCG/3, FlexBus = MCG/3, Flash clock= MCG/8SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2)| SIM_CLK

13、DIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(7);/從新存FMC_PFAPR的原始值FMC_PFAPR = temp_reg;/ 設(shè)置 VCO 分頻器，使能 PLL為 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30);/VDIV = 31 (x54)/VDIV = 26 (x50)while (!(MCG_S & MCG_S_PLLST_MASK);/ wait for PLL status bit to setwhile (!(MCG_S

14、 & MCG_S_LOCK_MASK);/ Wait for LOCK bit to set/進(jìn)入PBE模式/通過清零CLKS位來進(jìn)入PEE模式/ CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0MCG_C1 &=MCG_C1_CLKS_MASK;/等待時(shí)鐘狀態(tài)位更新while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3);/SIM_CLKDIV2 |= SIM_CLKDIV2_USBDIV(1);/設(shè)置跟蹤時(shí)鐘為內(nèi)核時(shí)鐘SIM_SOPT2 |=

15、 SIM_SOPT2_TRACECLKSEL_MASK;/在PTA6引腳上使能 TRACE_CLKOU功能PORTA_PCR6 = ( PORT_PCR_MUX(Ox7);/使能FlexBus模塊時(shí)鐘SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;/在PTA6引腳上使能FB_CLKOUT功能P0RTC_PCR3 = ( PORT_PCR_MUX(Ox5);/鎖相環(huán)頻率為50/13*54=207.7M測(cè)試函數(shù)void pilinit207M(void )uin t32_t temp_reg;/使能IO端口時(shí)鐘SIM_SCGC5 |= (SIM_SCGC5_PORTA_MA

16、SK| SIM_SCGC5_PORTB_MASK| SIM_SCGC5_PORTC_MASK| SIM_SCGC5_PORTD_MASK| SIM_SCGC5_PORTE_MASK );/這里處在默認(rèn)的FEI模式/首先移動(dòng)到FBE模式MCG_C2 = 0;/MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;/初始化晶振后釋放鎖定狀態(tài)的振蕩器和GPIOSIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;LLWU_CS |= LLWU_CS_ACKISO_MASK;/選擇外部晶振，參考分頻器，清IREFS來啟

17、動(dòng)外部晶振1/011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is256.MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);/等待晶振穩(wěn)定/while (!(MCG_S & MCG_S_OSCINIT_MASK)/ 等待鎖相環(huán)初始化結(jié)束while (MCG_S & MCG_S_IREFST_MASK)/ 等待時(shí)鐘切換到外部參考時(shí)鐘while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_C

18、LKST_SHIFT) != 0x2)/進(jìn)入FBE模式，0x18=25 分頻=2M,0x08=15 分頻=3.333M0x09=16 分頻=3.125M,0x10=17 分頻=2.94M0x11=18 分頻=2.7778M0x12=19 分頻=2.63M,0x13=20 分頻=2.5MMCG_C5 = MCG_C5_PRDIV(0x0C);/確保MCG_C6處于復(fù)位狀態(tài)，禁止 LOLIE、PLL、和時(shí)鐘控制器，清 PLL VCO分頻器MCG_C6 = 0x0;/保存FMC_PFAPR當(dāng)前的值temp_reg = FMC_PFAPR;/通過M&PFD 置位MOPFD來禁止預(yù)取功能FMC_

19、PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK |FMC_PFAPR_M5PFD_MASK| FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK | FMC_PFAPR_M2PFD_MASK| FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;/設(shè)置系統(tǒng)分頻器MCG=PLL, core = MCG, bus = MCG/3, FlexBus = MCG/3, Flash clock= MCG/8SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0

20、) | SIM_CLKDIV1_OUTDIV2(2)| SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(7);/從新存FMC_PFAPR的原始值FMC_PFAPR = temp_reg;/ 設(shè)置 VCO 分頻器，使能 PLL為 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30);/VDIV = 31 (x54)/VDIV = 26 (x50)while (!(MCG_S & MCG_S_PLLST_MASK);/ wait for

21、PLL status bit to setwhile (!(MCG_S & MCG_S_LOCK_MASK);/ Wait for LOCK bit to set/進(jìn)入PBE模式/通過清零CLKS位來進(jìn)入PEE模式/ CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0MCG_C1 &=MCG_C1_CLKS_MASK;/等待時(shí)鐘狀態(tài)位更新while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3);SIM_CLKDIV2 |= SIM_CLKDIV2_

22、USBDIV(1);/設(shè)置跟蹤時(shí)鐘為內(nèi)核時(shí)鐘SIM_SOPT2 |= SIM_S0PT2_TRACECLKSEL_MASK;/在PTA6引腳上使能 TRACE_CLKOU功能PORTA_PCR6 = ( PORT_PCR_MUX(Ox7);/使能FlexBus模塊時(shí)鐘SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;/在PTA6引腳上使能FB_CLKOUT功能PORTC_PCR3 = ( PORT_PCR_MUX(0x5);/鎖相環(huán)頻率為50/15*54=180M測(cè)試函數(shù)void pilinit180M(void )uin t32_t temp_reg;/使能IO端口時(shí)鐘

23、SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK| SIM_SCGC5_PORTB_MASK| SIM_SCGC5_PORTC_MASK| SIM_SCGC5_PORTD_MASK| SIM_SCGC5_PORTE_MASK );/這里處在默認(rèn)的FEI模式/首先移動(dòng)到FBE模式MCG_C2 = 0;MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HG0_MASK | MCG_C2_EREFS_MASK;/初始化晶振后釋放鎖定狀態(tài)的振蕩器和GPIOSIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;LLWU_CS |= LLWU_CS_ACK

24、ISO_MASK;/選擇外部晶振，參考分頻器，清IREFS來啟動(dòng)外部晶振/011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is256.MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);/等待晶振穩(wěn)定/while (!(MCG_S & MCG_S_OSCINIT_MASK)/ 等待鎖相環(huán)初始化結(jié)束while (MCG_S & MCG_S_IREFST_MASK)/ 等待時(shí)鐘切換到外部參考時(shí)鐘while (MCG_S & MCG_

25、S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2)/進(jìn)入FBE模式，0x18=25 分頻=2M,0x08=15 分頻=3.333M0x09=16 分頻=3.125M,0x10=17 分頻=2.94M/0x11=18 分頻=2.7778M0x12=19分頻=2.63M,0x13=20分頻=2.5MMCG_C5 = MCG_C5_PRDIV(0x0e);/確保MCG_C6處于復(fù)位狀態(tài)，禁止 LOLIE、PLL、和時(shí)鐘控制器，清 PLL VCO分頻器MCG_C6 = 0x0;/保存FMC_PFAPR當(dāng)前的值temp_reg = FMC_PFAPR;/通

26、過M&PFD 置位M0PFD來禁止預(yù)取功能FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK |FMC_PFAPR_M5PFD_MASK| FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK |FMC_PFAPR_M2PFD_MASK| FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;/設(shè)置系統(tǒng)分頻器MCG=PLL, core = MCG, bus = MCG/3, FlexBus = MCG/3, Flash clock= MCG/8SIM_CLK

27、DIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2)| SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(7);/從新存FMC_PFAPR的原始值FMC_PFAPR = temp_reg;/ 設(shè)置 VCO 分頻器，使能 PLL為 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30);/VDIV = 31 (x54)/VDIV = 26 (x50)while (!(MCG_S & M

28、CG_S_PLLST_MASK);/ wait for PLL status bit to setwhile (!(MCG_S & MCG_S_LOCK_MASK);/ Wait for LOCK bit to set/進(jìn)入PBE模式/通過清零CLKS位來進(jìn)入PEE模式/ CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=OMCG_C1 &=MCG_C1_CLKS_MASK;/等待時(shí)鐘狀態(tài)位更新while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3)

29、; SIM_CLKDIV2 |= SIM_CLKDIV2_USBDIV(1);/設(shè)置跟蹤時(shí)鐘為內(nèi)核時(shí)鐘SIM_SOPT2 |= SIM_SOPT2_TRACECLKSEL_MASK;/在PTA6引腳上使能 TRACE_CLKOU功能PORTA_PCR6 = ( PORT_PCR_MUX(Ox7);/使能FlexBus模塊時(shí)鐘SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;/在PTA6引腳上使能FB_CLKOUT功能PORTC_PCR3 = ( PORT_PCR_MUX(0x5);/鎖相環(huán)頻率為50/16*54=168.75M測(cè)試函數(shù)void pllinit168d75M

30、 (void )256.uin t32_t temp_reg;/使能IO端口時(shí)鐘SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK| SIM_SCGC5_PORTB_MASK| SIM_SCGC5_PORTC_MASK| SIM_SCGC5_PORTD_MASK| SIM_SCGC5_PORTE_MASK );/這里處在默認(rèn)的FEI模式/首先移動(dòng)到FBE模式MCG_C2 = 0;/MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG,/初始化晶振后釋放鎖定狀態(tài)的振蕩器和GPIOSIM_SCGC4 |= SIM_SCGC4_LLWU_

31、MASK;LLWU_CS |= LLWU_CS_ACKISO_MASK;/選擇外部晶振，參考分頻器，清IREFS來啟動(dòng)外部晶振/011 If RANGE = 0, Divide Factor is 8; for all other RANGE values,MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);/等待晶振穩(wěn)定/while (!(MCG_S & MCG_S_OSCINIT_MASK)C2_EREFS_MASK;Divide Factor is/等待鎖相環(huán)初始化結(jié)/等待時(shí)鐘切換到外部參while (MCG_S & MCG_S_IREFS

32、T_MASK)考時(shí)鐘while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2)/進(jìn)入FBE模式，0x18=25 分頻=2M,0x08=15 分頻=3.333M0x09=16 分頻=3.125M,0x10=17 分頻=2.94M/0x11=18 分頻=2.7778M/0x12=19 分頻=2.63M,/0x13=20 分頻=2.5MMCG_C5 = MCG_C5_PRDIV(0x0f);/確保MCG_C6處于復(fù)位狀態(tài)，禁止 LOLIE、PLL、和時(shí)鐘控制器，清 PLL VCO分頻器MCG_C6 = 0x0;/保

33、存FMC_PFAPR當(dāng)前的值temp_reg = FMC_PFAPR;/通過M&PFD 置位M0PFD來禁止預(yù)取功能FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK |FMC_PFAPR_M5PFD_MASK| FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK |FMC_PFAPR_M2PFD_MASK| FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;/設(shè)置系統(tǒng)分頻器MCG=PLL, core = MCG, bus = MCG/3, FlexB

34、us = MCG/3, Flash clock= MCG/8SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2)| SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(7);/從新存FMC_PFAPR的原始值FMC_PFAPR = temp_reg;/ 設(shè)置 VCO 分頻器，使能 PLL為 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30);/VDIV = 31 (x54)/

35、VDIV = 26 (x50)while (!(MCG_S & MCG_S_PLLST_MASK);/ wait for PLL status bit to setwhile (!(MCG_S & MCG_S_LOCK_MASK);/ Wait for LOCK bit to set/進(jìn)入PBE模式/通過清零CLKS位來進(jìn)入PEE模式/ CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0MCG_C1 &=MCG_C1_CLKS_MASK;/等待時(shí)鐘狀態(tài)位更新while (MCG_S & MCG_S_CLKST_MASK

36、) >> MCG_S_CLKST_SHIFT) != 0x3);/SIM_CLKDIV2 |= SIM_CLKDIV2_USBDIV(1);/設(shè)置跟蹤時(shí)鐘為內(nèi)核時(shí)鐘SIM_SOPT2 |= SIM_SOPT2_TRACECLKSEL_MASK;/在PTA6引腳上使能 TRACE_CLKOU功能PORTA_PCR6 = ( PORT_PCR_MUX(Ox7);/使能FlexBus模塊時(shí)鐘SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;/在PTA6引腳上使能FB_CLKOUT功能P0RTC_PCR3 = ( PORT_PCR_MUX(Ox5);/鎖相環(huán)頻率為50

37、/18*54=150M測(cè)試函數(shù)void pilinit150M(void )uin t32_t temp_reg;/使能IO端口時(shí)鐘SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK| SIM_SCGC5_PORTB_MASK| SIM_SCGC5_PORTC_MASK| SIM_SCGC5_PORTD_MASK| SIM_SCGC5_PORTE_MASK );/這里處在默認(rèn)的FEI模式/首先移動(dòng)到FBE模式MCG_C2 = 0;/MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;/初始化晶振后釋放鎖

38、定狀態(tài)的振蕩器和GPIOSIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;LLWU_CS |= LLWU_CS_ACKISO_MASK;/選擇外部晶振，參考分頻器，清IREFS來啟動(dòng)外部晶振1/011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is256.MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);/等待晶振穩(wěn)定/while (!(MCG_S & MCG_S_OSCINIT_MASK)/ 等待鎖相環(huán)初始化結(jié)束while (

39、MCG_S & MCG_S_IREFST_MASK)/ 等待時(shí)鐘切換到外部參考時(shí)鐘while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2)/進(jìn)入FBE模式，0x18=25 分頻=2M,0x11=18 分頻=2.7778M0x12=19 分頻=2.63M,0x13=20 分頻=2.5MMCG_C5 = MCG_C5_PRDIV(0x11);/確保MCG_C6處于復(fù)位狀態(tài)，禁止 LOLIE、PLL、和時(shí)鐘控制器，清 PLL VCO分頻器MCG_C6 = 0x0;/保存FMC_PFAPR當(dāng)前的值temp_

40、reg = FMC_PFAPR;/通過M&PFD 置位M0PFD來禁止預(yù)取功能FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK |FMC_PFAPR_M5PFD_MASK| FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK | FMC_PFAPR_M2PFD_MASK| FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;/設(shè)置系統(tǒng)分頻器MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash

41、clock= MCG/8SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1)| SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(7);/從新存FMC_PFAPR的原始值FMC_PFAPR = temp_reg;/ 設(shè)置 VCO 分頻器，使能 PLL為 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30);/VDIV = 31 (x54)/VDIV = 26 (x50)whi

42、le (!(MCG_S & MCG_S_PLLST_MASK);/ wait for PLL status bit to setwhile (!(MCG_S & MCG_S_LOCK_MASK);/ Wait for LOCK bit to set/進(jìn)入PBE模式/通過清零CLKS位來進(jìn)入PEE模式/ CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0MCG_C1 &=MCG_C1_CLKS_MASK;/等待時(shí)鐘狀態(tài)位更新while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_C

43、LKST_SHIFT) != 0x3);/SIM_CLKDIV2 |= SIM_CLKDIV2_USBDIV(1);/設(shè)置跟蹤時(shí)鐘為內(nèi)核時(shí)鐘SIM_S0PT2 |= SIM_S0PT2_TRACECLKSEL_MASK;/在PTA6引腳上使能 TRACE_CLKOU功能P0RTA_PCR6 = ( PORT_PCR_MUX(0x7);/使能FlexBus模塊時(shí)鐘SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;/在PTA6引腳上使能FB_CLKOUT功能PORTC_PCR3 = ( PORT_PCR_MUX(0x5);/鎖相環(huán)頻率為 50/19*55=144.738642

44、1M測(cè)試函數(shù)void pllinit144M(void )uin t32_t temp_reg;/使能IO端口時(shí)鐘SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK| SIM_SCGC5_PORTB_MASK| SIM_SCGC5_PORTC_MASK| SIM_SCGC5_PORTD_MASK| SIM_SCGC5_PORTE_MASK );/這里處在默認(rèn)的FEI模式/首先移動(dòng)到FBE模式MCG_C2 = 0;/MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;/初始化晶振后釋放鎖定狀態(tài)的振蕩器和G

45、PIOSIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;LLWU_CS |= LLWU_CS_ACKISO_MASK;/選擇外部晶振，參考分頻器，清IREFS來啟動(dòng)外部晶振/011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is256.MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);/等待晶振穩(wěn)定/while (!(MCG_S & MCG_S_OSCINIT_MASK)/ 等待鎖相環(huán)初始化結(jié)束while (MCG_S &

46、; MCG_S_IREFST_MASK)/ 等待時(shí)鐘切換到外部參考時(shí)鐘while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2)/進(jìn)入FBE模式，0x18=25分頻=2M,0x11=18分頻=2.7778M/0x12=19 分頻=2.63M,/0x13=20 分頻=2.5MMCG_C5 = MCG_C5_PRDIV(0x12);/確保MCG_C6處于復(fù)位狀態(tài)，禁止 LOLIE、PLL、和時(shí)鐘控制器，清 PLL VCO分頻器MCG_C6 = 0x0;/保存FMC_PFAPR當(dāng)前的值temp_reg = FMC_

47、PFAPR;/通過M&PFD 置位MOPFD來禁止預(yù)取功能FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK |FMC_PFAPR_M5PFD_MASK| FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK |FMC_PFAPR_M2PFD_MASK| FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;/設(shè)置系統(tǒng)分頻器/MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG

48、/6SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1)| SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(5);/從新存FMC_PFAPR的原始值FMC_PFAPR = temp_reg;/ 設(shè)置 VCO 分頻器，使能 PLL為 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(31);/VDIV = 31 (x55)/VDIV = 26 (x50)while (!(MCG_

49、S & MCG_S_PLLST_MASK);/ wait for PLL status bit to setwhile (!(MCG_S & MCG_S_LOCK_MASK);/ Wait for LOCK bit to set/進(jìn)入PBE模式/通過清零CLKS位來進(jìn)入PEE模式/ CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=OMCG_C1 &=MCG_C1_CLKS_MASK;/等待時(shí)鐘狀態(tài)位更新while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT

50、) != 0x3); /SIM_CLKDIV2 |= SIM_CLKDIV2_USBDIV(1);/設(shè)置跟蹤時(shí)鐘為內(nèi)核時(shí)鐘SIM_SOPT2 |= SIM_SOPT2_TRACECLKSEL_MASK;/在PTA6引腳上使能 TRACE_CLKOU功能PORTA_PCR6 = ( PORT_PCR_MUX(Ox7);/使能FlexBus模塊時(shí)鐘SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;/在PTA6引腳上使能FB_CLKOUT功能PORTC_PCR3 = ( PORT_PCR_MUX(0x5);/鎖相環(huán)頻率為137.5M測(cè)試函數(shù)void pilinit1375M(v

51、oid )uin t32_t temp_reg;/使能IO端口時(shí)鐘SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK| SIM_SCGC5_PORTB_MASK| SIM_SCGC5_PORTC_MASK| SIM_SCGC5_PORTD_MASK| SIM_SCGC5_PORTE_MASK );/這里處在默認(rèn)的FEI模式/首先移動(dòng)到FBE模式MCG_C2 = 0;/MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;/初始化晶振后釋放鎖定狀態(tài)的振蕩器和GPIOSIM_SCGC4 |= SIM_SCGC

52、4_LLWU_MASK;LLWU_CS |= LLWU_CS_ACKISO_MASK;/選擇外部晶振，參考分頻器，清IREFS來啟動(dòng)外部晶振/011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor isMCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);/等待晶振穩(wěn)定/while (!(MCG_S & MCG_S_OSCINIT_MASK)/ 等待鎖相環(huán)初始化結(jié)束while (MCG_S & MCG_S_IREFST_MASK)/ 等待時(shí)鐘切換

53、到外部參考時(shí)鐘while (MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2)/進(jìn)入FBE模式，0x18=25分頻=2M,0x11=18分頻=2.7778M/0x12=19 分頻=2.63M,/0x13=20 分頻=2.5MMCG_C5 = MCG_C5_PRDIV(0x13);/確保MCG_C6處于復(fù)位狀態(tài)，禁止 LOLIE、PLL、和時(shí)鐘控制器，清 PLL VCO分頻器MCG_C6 = 0x0;/保存FMC_PFAPR當(dāng)前的值temp_reg = FMC_PFAPR;/通過M&PFD 置位MOPFD來禁

54、止預(yù)取功能FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK |FMC_PFAPR_M5PFD_MASK| FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK | FMC_PFAPR_M2PFD_MASK| FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;/設(shè)置系統(tǒng)分頻器MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/6SIM_CLKDIV1 = SIM_CLKDIV1_

55、OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1)| SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(5);/從新存FMC_PFAPR的原始值FMC_PFAPR = temp_reg;/ 設(shè)置 VCO 分頻器，使能 PLL為 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(31);/VDIV = 31 (x55)/VDIV = 26 (x50)while (!(MCG_S & MCG_S_PLLST_MASK);/ wait for PLL status bit to setwhile (!(MCG_S & MCG_S_LOCK_MASK);/ Wait for LOCK bit to set/進(jìn)入PBE模式/通過清零CL

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