7相關元器件adc08313238英文手冊

1、© 1999 National Semiconductor CorporationDS005583ADC0831/ADC0832/ADC0834/ADC0838 8-Bit Serial I/O A/D Converters with Multiplexer OptionsJuly 1999ADC0831/ADC0832/ADC0834/ADC08388-Bit Serial I/O A/D Converters with Multiplexer OptionsGeneral Descriptionn Operates ratiometrically or with 5 VDC vo

2、ltage referenceThe ADC0831 series are 8-bit successive approximation A/Dn No zero or full-scale adjust requiredconverters with a serial I/O and configurable input multiplex-ers with up to 8 channels. The serial I/O is configured ton 2-, 4- or 8-channel multiplexer options with address logiccomply wi

3、th the NSC MICROWIRE serial data exchangen Shunt regulator allows operation with high voltagestandard for easy interface to the COPS family of proces-suppliessors, and can interface with standard shift registers or µPs.n 0V to 5V input range with single 5V power supplyThe 2-, 4- or 8-channel mu

4、ltiplexers are software configuredn Remote operation with serial digital data link for single-ended or differential inputs as well as channel as-n TTL/MOS input/output compatiblesignment.n 0.3" standard width, 8-, 14- or 20-pin DIP packageThe differential analog voltage input allows increasing

5、then 20 Pin Molded Chip Carrier Package (ADC0838 only) common-mode rejection and offsetting the analog zero inputn Surface-Mount Packagevoltage value. In addition, the voltage reference input can beadjusted to allow encoding any smaller analog voltage spanKey Specificationsto the full 8 bits of reso

6、lution.n Resolution8 BitsFeaturesn Total Unadjusted Error±12 LSB and ±1 LSBn Single Supply5 VDCn NSC MICROWIRE compatible direct interface ton Low Power15 mWCOPS family processorsn Conversion Time32 µsn Easy interface to all microprocessors, or operates“stand-alone”Typical Application

7、DS005583-1TRI-STATE® is a registered trademark of National Semiconductor Corporation. COPS and MICROWIRE are trademarks of National Semiconductor Corporation.2Connection DiagramsADC0838 8-Channel MuxSmall Outline/Dual-In-Line PackageADC0834 4-Channel MUXADC0832 2-Channel MUX (WM and N)Small Out

8、line/Dual-In-Line PackageDual-In-Line Package (N)(WM and N)DS005583-31COM internally connected to GND. VREF internally connected to VCC. Top ViewDS005583-30COM internally connected to A GNDTop ViewTop ViewDS005583-8Top ViewTop ViewADC0832 2-Channel MUXADC0831 SingleSmall Outline Package (WM)Differen

9、tial InputADC0831 Single Differential InputDual-In-Line Package (N)Small Outline Package (WM)DS005583-32Top ViewDS005583-41Top ViewDS005583-42Top ViewADC0838 8-Channel MUX Molded Chip Carrier (PCC) Package (V)DS005583-333Ordering InformationPart NumberAnalog Input ChannelsTotal Unadjusted ErrorPacka

10、geTemperature RangeADC0831CCN ADC0831CCWM1±1Molded (N) SO(M)0C to +70C0C to +70CADC0832CIWM ADC0832CCN ADC0832CCWM2±1SO(M)Molded (N) SO(M)40C to +85C 0C to +70C0C to +70CADC0834BCN4±12Molded (N)0C to +70CADC0834CCN ADC0834CCWM±1Molded (N) SO(M)0C to +70C0C to +70CADC0838BCV8±

11、;12PCC (V)0C to +70CADC0838CCV ADC0838CCN ADC0838CIWM ADC0838CCWM±1PCC (V)Molded (N) SO(M)SO(M)0C to +70C0C to +70C40C to +85C 0C to +70CSee NS Package Number M14B, M20B, N08E, N14A, N20A or V20A4Absoluteum Ratings (Notes 1, 2)Lead Temperature (Soldering 10 sec.)If Military/Aerospace specified

12、devices are required,Dual-In-Line Package (Plastic)260Cplease contact the National Semiconductor Sales Office/Molded Chip Carrier PackageDistributors for availability and specifications.Vapor Phase (60 sec.)215CCurrent into V+ (Note 3)15 mAInfrared (15 sec.)220CSupply Voltage, V(Note 3)6.5VESD Susce

13、ptibility (Note 5)2000VCCVoltageOperating Ratings (Notes 1, 2)Logic Inputs0.3V to VCC + 0.3VAnalog Inputs0.3V to VCC + 0.3VSupply Voltage, VCC4.5 VDC to 6.3 VDC Input Current per Pin (Note 4)±5 mATemperature RangeTMIN£TA£TMAX Package±20 mAADC0832/8CIWM40C to +85CStorage Temperatu

14、re65C to +150CADC0834BCN,Package DissipationADC0838BCV,at TA=25C (Board Mount)0.8WADC0831/2/4/8CCN, ADC0838CCV,ADC0831/2/4/8CCWM0C to +70CConverter and Multiplexer Electrical Characteristics The following specifications apply for VCC = V+ = VREF = 5V, VREF £ VCC +0.1V, TA = Tj = 25C, and fCLK =

15、 250 kHz unless otherwise specified. Boldface limits apply from TMIN to TMAX.CONVERTER AND MULTIPLEXER CHARACTERISTICSTotal Unadjusted Error ADC0838BCV ADC0834BCN ADC0838CCV ADC0831/2/4/8CCN ADC0831/2/4/8CCWM ADC0832/8CIWMVREF=5.00 V(Note 6)±1±12±12±1±1±1±12±1

16、2±1±1±1LSB(Max)Minimum Reference Input(Note 7)3.51.33.51.31.3kWum ReferenceInput(Note 7)3.55.93.55.45.9kWum Common-Mode Input Range (Note 8)VCC +0.05VCC +0.05VCC+0.05VMinimum Common-Mode Input Range (Note 8)GND 0.05GND 0.05GND0.05VDC Common-Mode Error±1/16±14±1/16±

17、14±14LSBChange in zero error from VCC=5V to internal zener operation (Note 3)15 mA into V+ VCC=N.C. VREF=5V111LSBVZ, internalMINdiode breakdownMAX (at V+) (Note 3)15 mA into V+6.38.56.38.56.38.5VPower Supply SensitivityVCC=5V±5%±1/16±14±14±1/16±14±14LSBIOFF, O

18、ff Channel Leakage Current (Note 9)On Channel=5V, Off Channel=0V0.210.21µAOn Channel=0V, Off Channel=5V+0.2+1+0.2+1µAParameterConditionsCIWM DevicesBCV, CCV, CCWM, BCNand CCN DevicesUnitsTyp(Note 12)Tested Limit (Note 13)Design Limit (Note 14)Typ(Note 12)Tested Limit (Note 13)Design Limit

19、(Note 14)5Converter and Multiplexer Electrical Characteristics The following specifications apply for VCC = V+ = VREF = 5V, VREF £ VCC +0.1V, TA = Tj = 25C, and fCLK = 250 kHz unless otherwise specified. Boldface limits apply from TMIN to TMAX. (Continued)CONVERTER AND MULTIPLEXER CHARACTERISTI

20、CSDIGITAL AND DC CHARACTERISTICSAC CharacteristicsThe following specifications apply for VCC = 5V, tr = tf = 20 ns and 25C unless otherwise specified.ParameterConditionsTyp(Note 12)Tested Limit (Note 13)Design Limit (Note 14)Limit UnitsfCLK, Clock FrequencyMin Max10400kHz kHztC, Conversion TimeNot i

21、ncluding MUX Addressing Time81/fCLKClock Duty CycleMin(Note 10)Max4060%tSET-UP, CS Falling Edge or Data Input Valid to CLK Rising Edge250nstHOLD, Data Input Valid after CLK Rising Edge90nsVIN(1), Logical “1” Input Voltage (Min)VCC=5.25V2.02.02.0VVIN(0), Logical “0” Input Voltage (Max)VCC=4.75V0.80.8

22、0.8VIIN(1), Logical “1” Input Current (Max)VIN=5.0V0.00510.00511µAIIN(0), Logical “0” Input Current (Max)VIN=0V0.00510.00511µAVOUT(1), Logical “1” Output Voltage (Min)VCC=4.75V IOUT=360 µA IOUT=10 µA2.44.52.44.52.44.5V VVOUT(0), Logical “0” Output Voltage (Max)VCC=4.75V IOUT=1.6

23、mA0.40.40.4VIOUT, TRI-STATE OutputCurrent (Max)VOUT=0V VOUT=5V0.10.1330.10.13+33+3µA µAISOURCE, Output Source Current (Min)VOUT=0V146.5147.56.5mAISINK, Output Sink Current (Min)VOUT=VCC168.0169.08.0mAICC, Supply Current (Max) ADC0831, ADC0834, ADC08380.92.50.92.52.5mAADC0832Includes Ladder

24、 Current2.36.52.36.56.5mAION, On Channel Leakage Current (Note 9)On Channel=0V, Off Channel=5V0.210.21µAOn Channel=5V, Off Channel=0V+0.2+1+0.2+1µAParameterConditionsCIWM DevicesBCV, CCV, CCWM, BCNand CCN DevicesUnitsTyp(Note 12)Tested Limit (Note 13)Design Limit (Note 14)Typ(Note 12)Teste

25、d Limit (Note 13)Design Limit (Note 14)6AC Characteristics (Continued)The following specifications apply for VCC = 5V, tr = tf = 20 ns and 25C unless otherwise specified.Note 1: Absoluteum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not

26、 apply when operating the device beyond its specified operating conditions.Note 2: All voltages are measured with respect to the ground plugs.Note 3: Internal zener diodes (6.3 to 8.5V) are connected from V+ to GND and VCC to GND. The zener at V+ can operate as a shunt regulator and is connected to

27、VCC via a conventional diode. Since the zener voltage equals the A/Ds breakdown voltage, the diode insures that VCC will be below breakdown when the device is powered from V+. Functionality is therefore guaranteed for V+ operation even though the resultant voltage at VCC may exceed the specified Abs

28、olute Max of 6.5V. It is recommended that a resistor be used to limit the max current into V+. (See Figure 3 in Functional Description Section 6.0)Note 4: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V or VIN > V+) the absolute value of current at that pin shou

29、ld be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.Note 5: Human body m, 100 pF discharged through a 1.5 kW resistor.Note 6: Total unadjusted error includes offset, full-scale, lineari

30、ty, and multiplexer errors.Note 7: Cannot be tested for ADC0832.Note 8: For VIN()³VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode

31、drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. T

32、his means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature varia- tions, initial tolera

33、nce and loading.Note 9: Leakage current is measured with the clock not switching.Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the minimum, time the clock is high or the mi

34、nimum time the clock is low must be at least 1 µs. Theum time the clock can be high is 60 µs. The clock can be stopped when low so long as the analog input voltage remains stable.Note 11: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an a

35、dditional delay is built in (see Block Diagram) to allow for comparator response time.Note 12: Typicals are at 25C and represent most likely parametric norm.Note 13: Tested limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level).Note 14: Guaranteed but not 100% production tested. Th

36、ese limits are not used to calculate outgoing quality levels.Typical Performance CharacteristicsUnadjusted Offset ErrorLinearity Error vs VREFLinearity Error vs vs VREF VoltageVoltageTemperatureDS005583-43DS005583-44DS005583-45ParameterConditionsTyp(Note 12)Tested Limit (Note 13)Design Limit (Note 1

37、4)Limit Unitstpd1, tpd0 CLK Falling Edge to Output Data Valid (Note 11)CL=100 pFData MSB First Data LSB First6502501500600ns nst1H, t0H, Rising Edge of CS to Data Output and SARS HiZCL=10 pF, RL=10k(see TRI-STATE® Test Circuits)125250nsCL=100 pf, RL=2k500nsCIN, Capacitance of Logic Input5pFCOUT

38、, Capacitance of Logic Outputs5pF7Typical Performance Characteristics (Continued)Linearity Error vs fCLKPower Supply Current vsOutput Current vsTemperature (ADC0838,Temperature ADC0831, ADC0834)DS005583-46DS005583-48DS005583-47Note: For ADC0832 add IREF.Power Supply Current vs fCLKDS005583-29Leakage

39、 Current Test CircuitDS005583-38TRI-STATE Test Circuits and Waveformst1Ht0HDS005583-49DS005583-50t1Ht0HDS005583-51DS005583-52Timing DiagramsData Input TimingData Output TimingDS005583-24DS005583-25ADC0831 Start Conversion TimingDS005583-269Timing Diagrams (Continued)ADC0831 TimingDS005583-27*LSB fir

40、st output not available on ADC0831.ADC0832 TimingDS005583-28ADC0834 TimingDS005583-5Timing Diagrams (Continued)10ADC0838 TimingDS005583-6*Make sure clock edge #18 clocks in the LSB before SE is taken lowADC0838 Functional Block Diagram11DS005583-7*Some of these functions/pins are not available with

41、other options.Note 1: For the ADC0834, D1 is input directly to the D input of SELECT 1. SELECT 0 is forced to a “1”. For the ADC0832, DI is input directly to the DI input of ODD/SIGN. SELECT 0 is forced to a “0” and SELECT 1 is forced to a “1”.12Functional Description1.0 MULTIPLEXER ADDRESSINGThe de

42、sign of these converters utilizes a sample-data com-In the differential case, it also assigns the polarity of the parator structure which provides for a differential analog in-channels. Differential inputs are restricted to adjacent chan- put to be converted by a successive approximation routine.nel

43、 pairs. For example channel 0 and channel 1 may be se- The actual voltage converted is always the difference be-lected as a different pair but channel 0 or 1 cannot act differ-tween an assigned “+” input terminal and a “” input terminal.entially with any other channel. In addition to selectingThe po

44、larity of each input terminal of the pair being con-differential mode the sign may also be selected. Channel 0 verted indicates which line the converter expects to be themay be selected as the positive input and channel 1 as the most positive. If the assigned “+” input is less than the “” in-negativ

45、e input or vice versa. This programmability is best il- put the converter responds with an all zeros output code.lustrated by the MUX addressing codes shown in the follow- A unique input multiplexing scheme has been utilized to pro-ing tables for the various product options.vide multiple analog chan

46、nels with software-configurableThe MUX address is shifted into the converter via the DI line.single-ended, differential, or a new pseudo-differential optionBecause the ADC0831 contains only one differential input which will convert the difference between the voltage at anychannel with a fixed polari

47、ty assignment, it does not require analog input and a common terminal. The analog signal con-addressing.ditioning required in transducer-based data acquisition sys-The common input line on the ADC0838 can be used as a tems is significantly simplified with this type of input flexibility.pseudo-differ

48、ential input. In this mode, the voltage on this pin One converter package can now handle ground referencedis treated as the “” input for any of the other input channels. inputs and true differential inputs as well as signals withThis voltage does not have to be analog ground; it can be some arbitrar

49、y reference voltage.any reference potential which is common to all of the inputs. A particular input configuration is assigned during the MUXThis feature is most useful in single-supply application whereaddressing sequence, prior to the start of a conversion. Thethe analog circuitry may be biased up

50、 to a potential otherMUX address selects which of the analog inputs are to bethan ground and the output signals are all referred to this enabled and whether this input is single-ended or differential.potential.TABLE 1. Multiplexer/Package OptionsPart NumberNumber of Analog ChannelsNumber of Package

51、PinsSingle-EndedDifferentialADC0831118ADC0832218ADC08344214ADC0838842013Functional Description (Continued)TABLE 2. MUX Addressing: ADC0838Single-Ended MUX ModeTABLE 3. MUX Addressing: ADC0838Differential MUX ModeTABLE 4. MUX Addressing: ADC0834 Single-Ended MUX ModeCOM is internally tied to A GNDTAB

52、LE 5. MUX Addressing: ADC0834 Differential MUX ModeMUX AddressChannel #SGL/ DIFODD/ SIGNSELECT01231000+001+010+011+MUX AddressChannel #SGL/ DIFODD/ SIGNSELECT01231100+101+110+111+MUX AddressAnalog Differential Channel-Pair #SGL/ DIFODD/ SIGNSELECT012310012345670000+0001+0010+0011+0100+0101+0110+0111+MUX AddressAnalog