數(shù)字邏輯設(shè)計(jì)及應(yīng)用教學(xué)課件：8-1 時(shí)序電路的設(shè)計(jì)實(shí)踐xin

1、c h a p t e r 8Sequential Logic DesignPractices時(shí)序邏輯設(shè)計(jì)實(shí)踐數(shù)字邏輯設(shè)計(jì)及應(yīng)用Chapter 88.1 Sequential Circuit Documentation Standards(時(shí)序電路文檔標(biāo)準(zhǔn))8.1.4 Timing Diagrams (定時(shí)圖) and Specifications8.2 Latches and Flip-Flops8.2.1 SSI Latches and Flip-Flops(SSI型鎖存器和觸發(fā)器)applications：8.2.2 Switch Debouncing開(kāi)關(guān)消抖、 8.2.4 Bus Ho

2、lder Circuit總線保持 8.2.5 Multibit Registers and Latches多位寄存器和鎖存器CLOCK觸發(fā)器輸出組合電路輸出觸發(fā)器輸入建立時(shí)間容限Hold-time marginSetup-time margin8.2 Latches and Flip-Flops( 鎖存器和觸發(fā)器)SSI Latches and Flip-Flops1Q 1Q2Q2Q3Q3Q4Q4Q1,2C1D2D3,4C3D4D74x375D LatchesPRD Q CLK QCLR74x74PRJ Q CLK K QCLR74x109PRJ Q CLK K QCLR74x112Switc

3、h Debouncing (開(kāi)關(guān)消抖)+5VSW_LDSWPush(開(kāi)關(guān)閉合)SW_LDSWPush(開(kāi)關(guān)閉合)First Contact(閉合第1次接觸)ContactBounce(觸點(diǎn)抖動(dòng))SW_LDSWIdeal Case (理想情況)SW_LSW0011SW_LSW0011Push(開(kāi)關(guān)閉合)0011SW_LSW0011SW_LSW1100SW_LSWDSWPush(開(kāi)關(guān)閉合)why this circuit should not be used with the high-speed CMOS devices?(為什么不應(yīng)該同高速CMOS器件一起使用？)QQLS QR Q+5VBus

4、 Holder Circuit (總線保持電路)ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSRC0SRC1SRC2P0P1P7SDATA4-bit Register(4位寄存器74x175)6位寄存器74x1741D2D3D4DCLKCLR_L8-bit Register74x374（三態(tài)輸出）OE輸出使能74x377（時(shí)鐘使能）74x273（異步清零）CLK74x374（輸出使能）74x377（Clock Enable, 時(shí)鐘使能）ENEN二選一多路復(fù)用結(jié)構(gòu) register and latch 寄存器：edge trigger chract

5、erastic 邊沿觸發(fā)特性 鎖存器：C有效期間輸出跟隨輸入變化74x374輸出使能8位寄存器74x373輸出使能8位鎖存器8.4 Counters (計(jì)數(shù)器)Counter(計(jì)數(shù)器)(P710)The name counter is generally used for any clocked sequential circuit whose state diagram contains a single cycle, as in Figure 8-26. The modulus of a counter is the number of states in the cycle. A cou

6、nter with m states is called a modulo-m counter or, sometimes, a divide-by-m counter. A counter with a nonpower-of-2 modulus has extra states that are not used in normal operation. 計(jì)數(shù)器的分類按時(shí)鐘：同步、異步按計(jì)數(shù)方式：加法、減法、可逆按編碼方式：二進(jìn)制、十進(jìn)制BCD碼、循環(huán)碼計(jì)數(shù)器的功能計(jì)數(shù)、分頻、定時(shí)、產(chǎn)生脈沖序列、數(shù)字運(yùn)算本節(jié)內(nèi)容行波計(jì)數(shù)器、同步計(jì)數(shù)器MSI型計(jì)數(shù)器及其應(yīng)用二進(jìn)制計(jì)數(shù)器狀態(tài)的譯碼8.4.1

7、Ripple CountersAN n-bit binary counter can be constructed with just n flip-flops and no other components , for any value of n. 2bits binary counters normal binary counting sequence is 00-01-10-11-0010108.4.1 Ripple Counterswhen a particular bit changes from 1 to 0, it generates a carry to the next m

8、ost significant bit. The counter is called a ripple counter because the carry information ripples from the less significant bits to the more significant bits, one bit at a time. 00-01-10-11-008.4.1 Ripple Counters（行波計(jì)數(shù)器） use T flip-flopQ* = QQQT考慮二進(jìn)制計(jì)數(shù)順序：只有當(dāng)?shù)?i-1 位由10時(shí)，第 i 位才翻轉(zhuǎn)。CLKQQTQQTQQTQQTQ0Q1Q2

9、Q3T flip-flop changes state (toggles) on every rising edge of its clock input. Although a ripple counter requires fewer components than any other type ofbinary counter, it does so at a priceit is slower than any other type of binarycounter. In the worst case, when the most significant bit must chang

10、e, the outputis not valid until time n tTQ after the rising edge of CLK, where tTQ is thepropagation delay from input to output of a T flip-flop. Ripple CountersCLKQ0Q1Q2CLKQQTQQTQQTQQTQ0Q1Q2Q3速度慢，最壞情況，第n位要經(jīng)過(guò) ntTQ 的延遲時(shí)間 異步時(shí)序8.4.2 Synchronous Counters(同步計(jì)數(shù)器)A synchronous counter connects all of its f

11、lip-flop clock inputs to the same common CLK signal, so that all of the flip-flop outputs change at the same time, after only tTQ ns of delay. synchronous counter同步二進(jìn)制加法計(jì)數(shù)器1 0 1 1 0 1 1+ 11 0 1 1 1 0 0在多位二進(jìn)制數(shù)的末位加 1，僅當(dāng)?shù)?i 位以下的各位都為 1 時(shí)，第 i 位的狀態(tài)才會(huì)改變。最低位的狀態(tài)每次加1都要改變。EN QT Q 利用有使能端的 T 觸發(fā)器實(shí)現(xiàn)：Q* = ENQ + ENQ

12、 = EN Q通過(guò)EN端進(jìn)行控制，需要翻轉(zhuǎn)時(shí)，使 EN = 1 ENi = Qi-1 Qi-2 Q1 Q0EN0 = ? 1synchronous counter1CLKQ0Q1Q2C如何加入使能端？synchronous counter with enable input 有使能端的同步計(jì)數(shù)器CNTEN低位 LSB高位 MSB串行使能同步二進(jìn)制加法計(jì)數(shù)器1 0 1 1 0 1 1+ 11 0 1 1 1 0 0在多位二進(jìn)制數(shù)的末位加 1，僅當(dāng)?shù)?i 位以下的各位都為 1 時(shí)，第 i 位的狀態(tài)才會(huì)改變。最低位的狀態(tài)每次加1都要改變。對(duì)于D觸發(fā)器：Q* = DDi = (Qi-1 Q1 Q0)

13、QD Q CLK Q= EN Q考慮 T 觸發(fā)器：Q* = EN Q 利用 D 觸發(fā)器實(shí)現(xiàn)：D0 = 1 Q = Q8.4.3 MSI counters and applicationsMSI型計(jì)數(shù)器及應(yīng)用-同步4位二進(jìn)制計(jì)數(shù)器74x163CLR同步清零LD同步預(yù)置數(shù)RCO進(jìn)位輸出ENPENT使能端進(jìn)位輸出清零8.4.3 MSI Counters and Applications4位二進(jìn)制計(jì)數(shù)器74x16374x163的功能表01111CLK工作狀態(tài)同步清零同步置數(shù)保持保持,RCO=0計(jì)數(shù)CLR_LLD_LENP ENT0111 0 1 0 1 174x161異步清零CLKENClear an

14、d load functions同步清零和預(yù)置數(shù)Q0Q1Q2Q3D0D1D2D3LD_LCLR_LA計(jì)數(shù)功能的電路Qi* = (Qi-1 Q1 Q0) QQASynchronous clear and load functions同步清零和預(yù)置數(shù)功能0100000LD_LCLR_LA計(jì)數(shù)功能的電路Qi* = (Qi-1 Q1 Q0) QQA0010A0A11XSynchronous clear and load functions同步清零和預(yù)置數(shù)功能LD_LCLR_LA計(jì)數(shù)功能的電路Qi* = (Qi-1 Q1 Q0) QQAEnables and ripple carry out (RCO) signals使能信號(hào) 與進(jìn)位信號(hào) 10010QANQAN1ENP.ENT=1QANLD_LCLR_LB計(jì)數(shù)功能的電路Qi* = (Qi-1 Q1 Q0) QQB100101QAQBNEnables and ripple carry out (RCO) signals使能信號(hào) 與進(jìn)位信號(hào) Connections for the 74X163 to op