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1、 class exersise F = A,B,C,D ( 1, 3, 4, 5, 6, 7, 12, 14, 15 )Use the duality, find a minimal product-of-sums expression(和之積) for the following logic function F. 1、先將F轉(zhuǎn)為或與表達式, F= A,B,C,D (0,2,8,9,10,11,13)2、直接卡諾圖圈零化簡。 F=(B+D)(A+B) (A+C+D)F = A,B,C,D ( 1, 3, 4, 5, 6, 7, 12, 14, 15 )CDAB00 01 11 1000011
2、110000000011、先將F轉(zhuǎn)為或與表達式, 得F= A,B,C,D (0,2,8,9,10,11,13)2、求F的對偶式。 FD=A,B,C,D ( 2, 4, 5, 6, 7, 13, 15 )3、 FD的最簡與或式為: FD =BD+AB+ACD4、 FD的對偶式(FD)D =F。 F=(B+D)(A+B) (A+C+D)CDAB00 01 11 10000111101111111F = A,B,C,D ( 1, 3, 4, 5, 6, 7, 12, 14, 15 )21、先將F轉(zhuǎn)為或與表達式, 得F= A,B,C,D (0,2,8,9,10,11,13)2、求F的反演式。 F=A,
3、B,C,D (0, 2, 8, 9, 10, 11, 13)3、 F的最簡與或式為: F =BD+AB+ACD4、 F的反演式(F) =F。 F=(B+D)(A+B) (A+C+D)CDAB00 01 11 10000111101111111F = A,B,C,D ( 1, 3, 4, 5, 6, 7, 12, 14, 15 )3 C h a p t e r 6 Combinational Logic Design Practices 組合邏輯設(shè)計實踐We will studay.6.1 6.96.10 Combinational Logic Design
4、6.1 Documentation Standards Documentation(文檔):(P343)1、ciruit specification:線路的詳細說明。2、block diagram:方框圖.系統(tǒng)的主要功 能模塊及其基本互連的非正式圖示說明。3、schematic diagram:原理圖.4 . bill of materials(BOM):材料清單。5、timing diagram:定時圖(波形圖),輸入、輸出等波形的時間關(guān)系,包括其延時.Combinational Logic Design6. programmable logic device(PLD): 可編程 邏輯器件。
5、 field-programmable gate array(FPGA): 現(xiàn)場可編程門陣列。 application-specific integrated circuit(ASIC): 專用集成電路。7、circuit description:電路描述.8. bus:總線. 在框圖中總線用雙線或黑線表示。 總線的位數(shù)用斜杠加數(shù)字說明或總線名加方括號(例inbus31.0,inbus31:0)。6.1.1 block diagram(方框圖):(P345) 顯示系統(tǒng)的輸入、輸出、功能模塊內(nèi)部數(shù)據(jù)通路和重要控制信號. BUS :(總線) (P344)bus is a collection of
6、 two or more related signal lines. In a block diagram, buses are drawn with a double or heavy line.size denoted in the bus name INBUS31.0 or INBUS31:0). block diagramThe flow of control and data(控制流和數(shù)據(jù)流) in a block diagram should be clearly indicated. schematic diagram 原理圖6.1.2 Gate Symbols 邏輯門的符號A
7、small circle, called an inversion bubble6.1.3 Signal Names and Active Levels (信號名與有效電平)(P347)Each signal name should have an active level (有效電平)associated with it.A signal is active high(高電平有效)if it performs the named action or denotes the named condition when it is HIGH or 1. A signal is active low
8、(低電平有效)if it performs the named action or denotes the named condition when it is LOW or 0. Asserted(有效) , deasserted or nagated(無效) .6.1.3 Signal Names and Active LevelsActive lowActive highREADY-READY+ERROR.LERROR.HADDR15(L)ADDR15(H)RESET*RESETENABLEENABLEGOGO/RECEIVERECEIVETRANSMIT_LTRANSMIT Disti
9、nguish (區(qū)別) (P348)signal namesexpressions equations READYREADY , READY-LREADY-L=READY 6.1.4 Active Levels for Pins 引腳的有效電平(P349)(a) AND gate (74X08) (b) NAND gate(74X00)(c) NOR gate (74X02) (d) OR gate (74X32) Active Levels for Pins6.1.5 Bubble-to-Bubble Logic Design “ 圈到圈”的邏輯設(shè)計 (P351)6.1.6 Drawing
10、Layout (布局圖)A complete schematic page should be drawn with system inputs on the left and outputs on the right, and the general flow of signals should be from left to right. 手工畫圖計算機繪圖6.1.6 Drawing Layout (布局圖)1.A multipleschematic usually has a “flat” structure(平面結(jié)構(gòu)).2. Much like programs, schematics
11、 can also be constructed hierarchically, the “top-level” schematic. 層次展開(自頂向下)6.1.9 Additional Schematic InformationIC types type (IC型號)reference designators (參考標(biāo)志符)pin numbers (引腳). (P360-361)an open-drain or open-collector output. (漏極開路或集電極開路輸出) hysteresis. (滯后)6.2 Circuit Timing (電路定時)“Timing is
12、everything”in investing, in comedy, and yes, in digital design. 6.2.1 Timing Diagrams(定時圖)(P363)causality 6.2.2 Propagation Delaythe propagation delay of a signal path asthe time that it takes for a change at the input of the path to produce a change at the output of the path. from LOW to HIGH ( tpL
13、H) from HIGH to LOW (tpHL) 6.2.3 Timing Specifications 定時規(guī)格說明 Maximum. 最大延遲Typical 典型延遲Minimum 最小延遲worst-case delay 最壞情況延遲Tsetup 建立時間Thold 保持時間建立時間和保持時間建立時間:建立時間(Tsu:set up time)是指在時鐘沿到來之前數(shù)據(jù)從不穩(wěn)定到穩(wěn)定所需的時間,如果建立的時間不滿足要求那么數(shù)據(jù)將不能在這個時鐘上升沿被穩(wěn)定的打入觸發(fā)器; 建立時間和保持時間保持時間:保持時間(Th:hold time)是指數(shù)據(jù)穩(wěn)定后保持的時間,如果保持時間不滿足要求那么數(shù)
14、據(jù)同樣也不能被穩(wěn)定的打入觸發(fā)器。 NEXT CLASS 6.4 decoders6.5 encodersStandard MSI functions 中規(guī)模集成電路Decoder 譯碼器Encoder 編碼器Multiplexer 多路復(fù)用器parity circuit 奇偶校驗Comparator 比較器Adder subtractor 加法器減法器使能輸入編碼輸出編碼映射6.4 decoder 譯碼器6.4 decoder (P384) A decoder is a multiple-input(多輸入), multiple-output (多輸出)logic circuit that c
15、onverts coded inputs into coded outputs, where the input and output codes are different. The input code generally has fewer bits than the output code, and there is a one-to-one mapping(一對一映射) from input code words into output code words. In a one-to-one mapping, each input code word produces a diffe
16、rent output code word. The most commonly used input code is an n-bit binary code, where an n-bit word represents one of 2n different coded values . The most commonly used output code is a 1-out-of-m code, which contains m bits, where one bit is asserted at any time.使能輸入編碼輸出編碼映射6.4 Decoder(譯碼器)P3846.
17、4.1Binary Decoder (二進制譯碼器)n-to- 2n decoderThe most common decoder circuit is an n-to-2n decoder or binary decoder. Such a decoder has an n-bit binary input code and a 1-out-of-2n output code. 6.4.1Binary Decoder (二進制譯碼器)n-to- 2n decoder2-to-4 decoderY0Y1Y2Y3I0I1EN使能輸入編碼輸出編碼映射n位二進制碼2n中取1碼 0 X X 0 0 0
18、 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0inputsEN I1 I0outputs Y3 Y2 Y1 Y0 The truth table for a 2-to-4 binary decoder6.4.1Binary Decoder (二進制譯碼器)n-to- 2n decoder2-to-4 decoderY0Y1Y2Y3I0I1ENYi = EN mi使能輸入編碼輸出編碼映射n位二進制碼2n中取1碼 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1
19、1 1 1 0 0 0inputsEN I1 I0outputs Y3 Y2 Y1 Y0 The truth table for a 2-to-4 binary decoder當(dāng)輸入使能端(EN)有效時Yi = miDont care notation(無關(guān)符號)使能輸入編碼輸出編碼映射n位二進制碼2n中取1碼 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0inputsEN I1 I0outputs Y3 Y2 Y1 Y0 The truth table for a 2-to-4 binary deco
20、derDesign it !Y3=EN.I1.I0Y2=EN.I1.I0Y1=EN.I1.I0Y0=EN.I1.I02-to-4 decoder logic diagram. Example 1 :Position encoding for a 3-bit mechanical encoding disk Example 2:What is the BCD decoders structrure?I3I2I1I0ENY0Y9THE IMPORTANCE OF 74-SERIES LOGIC (P342)well look at commonly used 74-series ICs that
21、perform well structured logic functions. These parts are important building blocks in a digital designers toolbox . Even when you design for PLDs, FPGAs, or ASICs, understanding 74-series MSI functions is important. In PLD-based design, standard MSI functions can be used as a starting point for deve
22、loping logic equations for more specialized functions. And in FPGA and ASIC design, the basic building blocks (or “standard cells” or “macros”) provided by the FPGA or ASIC manufacturer may actually be defined as 74-series MSI functions, even to the extent of having similar descriptive numbers.6.4.2 Logic Symbols for Larger-Scale Elements
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