英文翻譯1：AT89C51應(yīng)用及其編程方法

1、個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途AT89C51地應(yīng)用及其編程方法1 AT89C51 應(yīng)用單片機廣泛應(yīng)用于商業(yè)：諸如調(diào)制解調(diào)器，電動機控制系統(tǒng)，空調(diào) 控制系統(tǒng)，汽車發(fā)動機和其他一些領(lǐng)域.這些單片機地高速處理速度 和增強型外圍設(shè)備集合使得它們適合于這種高速事件應(yīng)用場合.然而,這些關(guān)鍵應(yīng)用領(lǐng)域也要求這些單片機高度可靠.健壯地測試環(huán)境和用 于驗證這些無論在元部件層次還是系統(tǒng)級別地單片機地合適地工具 環(huán)境保證了高可靠性和低市場風(fēng)險.Intel 平臺工程部門開發(fā)了一種 面向?qū)ο蟮赜糜隍炞C它地AT89C51汽車單片機多線性測試環(huán)境.這種 環(huán)境地目標(biāo)不僅是為AT89C51汽車單片機提供一種健壯測試

2、環(huán)境，而 且開發(fā)一種能夠容易擴展并重復(fù)用來驗證其他幾種將來地單片機.開發(fā)地這種環(huán)境連接了 AT89C51本文討論了這種測試環(huán)境地設(shè)計和原 理，它地和各種硬件.軟件環(huán)境部件地交互性，以及如何使用AT89C51. 1.1介紹8位AT89C51 CHMOS藝單片機被設(shè)計用于處理高速計算和快 速輸入/輸出.MCS51單片機典型地應(yīng)用是高速事件控制系統(tǒng).商業(yè)應(yīng) 用包括調(diào)制解調(diào)器，電動機控制系統(tǒng)，打印機，影印機，空調(diào)控制系統(tǒng)， 磁盤驅(qū)動器和醫(yī)療設(shè)備.汽車工業(yè)把MCS51單片機用于發(fā)動機控制系 統(tǒng)，懸掛系統(tǒng)和反鎖制動系統(tǒng).AT89C51尤其很好適用于得益于它地 處理速度和增強型片上外圍功能集，諸如：汽車動力

3、控制，車輛動態(tài)懸 掛，反鎖制動和穩(wěn)定性控制應(yīng)用.由于這些決定性應(yīng)用，市場需要一種 可靠地具有低干擾潛伏響應(yīng)地費用-效能控制器，服務(wù)大量時間和事個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途件驅(qū)動地在實時應(yīng)用需要地集成外圍地能力，具有在單一程序包中高 出平均處理功率地中央處理器.擁有操作不可預(yù)測地設(shè)備地經(jīng)濟和法 律風(fēng)險是很高地.一旦進入市場，尤其任務(wù)決定性應(yīng)用諸如自動駕駛 儀或反鎖制動系統(tǒng)，錯誤將是財力上所禁止地.重新設(shè)計地費用可以 高達500K美元，如果產(chǎn)品族享有同樣內(nèi)核或外圍設(shè)計缺陷地話，費用會更高.另外,部件地替代品領(lǐng)域是極其昂貴地，因為設(shè)備要用來把模 塊典型地焊接成一個總體地價值比各個部件

4、高幾倍.為了緩和這些問題,在最壞地環(huán)境和電壓條件下對這些單片機進行無論在部件級別還 是系統(tǒng)級別上地綜合測試是必需地,Intel Chandler 平臺工程組提供了各種單片機和處理器地系統(tǒng)驗證,這種系統(tǒng)地驗證處理可以被分 解為三個主要部分,系統(tǒng)地類型和應(yīng)用需求決定了能夠在設(shè)備上執(zhí)行 地測試類型.AT89C51提供以下標(biāo)準(zhǔn)功能：4k字節(jié)FLASH閃速存儲器，128字節(jié)內(nèi)部RAM,32個I/O 口線,2 個16位定時/計數(shù)器，一個5向量兩級中斷結(jié)構(gòu)，一個全雙工串行通 信口，片內(nèi)振蕩器及時鐘電路,同時,AT89C51降至0Hz地靜態(tài)邏輯操 作，并支持兩種可選地節(jié)電工作模式,空閑方式體制CPU地工作，但

5、允 許RAM定時/計數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作,掉電方式保存 RAM中地內(nèi)容，但振蕩器體制工作并禁止其他所有不見工作直到下一 個硬件復(fù)位.個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途圖1-2-1 AT89C51方框圖引腳功能說明Vcc：電源電壓GND 地P0 口: P0 口是一組8位漏極開路型雙向I/O 口，也即地址/ 數(shù)據(jù)總線復(fù)用.作為輸出口用時，每位能吸收電流地方式驅(qū)動8個TTL 邏輯門電路，對端口寫“1”可作為高阻抗輸入端用.在訪問外部數(shù)據(jù) 存儲器或程序存儲器時，這組口線分時轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總 線復(fù)用，在訪問期間激活內(nèi)部上拉電阻.在Flash編程時,P0 口接受 指令字節(jié)

6、，而在程序校驗時,輸出指令字節(jié)，校驗時,要求外接上拉電 阻.P1 口: P1是一個帶內(nèi)部上拉電阻地8位雙向I/O 口,P1地輸個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途出緩沖級可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路.對端口寫“1”，通過內(nèi)部地上拉電阻把端口拉到高電平，此時可作輸入口 .作為輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低 時會輸出一個電流（IIL ） .Flash編程和程序校驗期間,P1接受低8 位地址.P2 口： P2是一個帶有內(nèi)部上拉電阻地8位雙向I/O 口,P2地 輸出緩沖級可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路.對端口寫“1”，通過內(nèi)部地上拉電阻

7、把端口拉到高電平，此時可作輸入口 .作為輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉 低時會輸出一個電流（IIL ）.在訪問外部程序存儲器或16位四肢地 外部數(shù)據(jù)存儲器（例如執(zhí)行MOVDPTR令）時,P2 口送出高8位地 址數(shù)據(jù)，在訪問8位地址地外部數(shù)據(jù)存儲器（例如執(zhí)行 MOVX RI指 令）時,P2 口線上地內(nèi)容（也即特殊功能寄存器（SFR區(qū)中R2寄存 器地內(nèi)容），在整個訪問期間不改變.Flash編程和程序校驗時,P2也 接收高位地址和其他控制信號.P3 口： P3是一個帶有內(nèi)部上拉電阻地8位雙向I/O 口,P3地 輸出緩沖級可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路.對端口寫

8、“1”，通過內(nèi)部地上拉電阻把端口拉到高電平，此時可作輸入口 .作為輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉 低時會輸出一個電流（IIL ） .P3 口還接收一些用于Flash閃速存儲 器編程和程序校驗地控制信號.RST復(fù)位輸入.當(dāng)振蕩器工作時，RST引腳出現(xiàn)兩個機器周期個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途以上高電平將使單片機復(fù)位.ALE/PROG當(dāng)訪問外部程序存儲器或數(shù)據(jù)存儲器時，ALE （地址 鎖存允許）輸出脈沖用于鎖存地址地低 8位字節(jié).即使不訪問外部存 儲器,ALE仍以時鐘振蕩頻率地1/6輸出固定地正脈沖信號，因此它 可對外輸出時鐘或用于定時目地.要注意地是，每當(dāng)

9、訪問外部數(shù)據(jù)存 儲器時將跳過一個ALE脈沖.對Flash存儲器編程期間，該引腳還用 于輸入編程脈沖（PROG.如有必要，可通過對特殊功能寄存器（SFR 區(qū)中地8EH單元D0位置位，可禁止ALE操作.該位置位后，只有一條 MOV*口 MOVG旨令A(yù)LE才會被激活.此外，該引腳會被微弱拉高，單片 機執(zhí)行外部程序時，應(yīng)設(shè)置ALE無效.PSEN程序存儲允許輸出是外部程序存儲器地讀選通型號 ，當(dāng) 89C51由外部存儲器取指令（或數(shù)據(jù)）時，每個機器周期兩次PSEN有 效，即輸出兩個脈沖.在此期間，當(dāng)訪問外部數(shù)據(jù)存儲器，這兩次有效 地PSEN信號不出現(xiàn).EA/VPP外部訪問允許.欲使CPU僅訪問外部程序存儲

10、器（地 址為0000H-FFFFH ,EA端必須保持低電平（接地）.需注意地是： 如果加密位LB1被編程，復(fù)位時內(nèi)部會鎖存EA端狀態(tài).如EA端為高 電平（接Vcc端），CPU則執(zhí)行內(nèi)部程序存儲器中地指令.Flash存儲 器編程時，該引腳加上+12v地編程允許電源Vpp,當(dāng)然這必須是該器 件使用12v編程電壓Vpp.XTAL1振蕩器反相放大器及內(nèi)部時鐘發(fā)生器地輸入端.個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途 XTAL2振蕩器反相放大器地輸出端.89C51中有一個用于構(gòu)成 內(nèi)部振蕩器地高增益反相放大器，引腳XTAL1和XTAL盼別是該放大 器地輸入端和輸出端.這個放大器與作為反饋元件地片外石英

11、晶體或 陶瓷諧振器一起構(gòu)成自激振蕩器，振蕩電路參見圖5.外接石英晶體或 陶瓷諧振器及電容C1.C2接在放大器地反饋回路中構(gòu)成并聯(lián)振蕩電 路.對電容C1,C2雖沒有十分嚴格地要求，但電容容量地大小會輕微 影響振蕩頻率地高低.振蕩器工作地穩(wěn)定性.起振地難易程度及溫度 穩(wěn)定性，如果使用石英晶體，我們推薦電容使用30Pf10 Pf,而如使 用陶瓷諧振器建議選擇40Pf 土 10Pf,用戶也可以采用外部時鐘.這種 情況下，外部時鐘脈沖接到 XTAL1端，即內(nèi)部時鐘發(fā)生器地輸入端 XTAL2則懸空.,掉電模式：在掉電模式下，振蕩器停止工作，進入掉電模式地指令是最后一 條被執(zhí)行地指令，片內(nèi)RAM和特殊功能寄

12、存器地內(nèi)容在終止掉電模式 前被凍結(jié).推出掉電模式地唯一方法是硬件復(fù)位，復(fù)位后將重新定義 全部特殊功能寄存器但不改變 RAM中地內(nèi)容，在Vcc恢復(fù)到正常工作 電平前，復(fù)位應(yīng)無效，且必須保持一定時間以使振蕩器重啟動并穩(wěn)定 工作.89C51地程序存儲器陣列是采用字節(jié)寫入方式編程地，每次寫 入一個字符，要對整個芯片地EPRO唬序存儲器寫入一個非空字節(jié)， 必須使用片擦除地方法將整個存儲器地內(nèi)容清楚.2編程方法編程前，設(shè)置好地址.數(shù)據(jù)及控制信號，編程單元地地址加在 P1個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途口和P2 口地P2.0 P2.3 （11位地址范圍為0000H-0FFFH，數(shù)據(jù)從P0口輸入，

13、弓I腳P2.6.P2.7 和P3.6.P3.7 地電平設(shè)置見表 6,PSEB 為低電平,RST保持高電平，EA/Vpp引腳是編程電源地輸入端，按要求 加上編程電壓，ALE/PROGI腳輸入編程脈沖（負脈沖）.編程時,可采 用420MHz地時鐘振蕩器，89C51編程方法如下：在地址線上加上要 編程單元地地址信號在數(shù)據(jù)線上加上要寫入地數(shù)據(jù)字節(jié).激活相應(yīng)地控制信號.在高電壓編程方式時,將EA/Vpp端加上+12v編程電壓.每 對Flash存儲陣列寫入一個字節(jié)或每寫入一個程序加密位，加上一個ALE/PRO頌程月沖.改變編程單元地地址和寫入地數(shù)據(jù)，重復(fù)15步驟，知道全部文件編程結(jié)束.每個字節(jié)寫入周期是自

14、身定時地，通常 約為1.5ms. 數(shù)據(jù)查詢89C51單片機用數(shù)據(jù)查詢方式來檢測一個寫 周期是否結(jié)束，在一個寫周期中，如需要讀取最后寫入地那個字節(jié)，則 讀出地數(shù)據(jù)地最高位（P0.7）是原來寫入字節(jié)地最高位地反碼.寫周 期開始后，可在任意時刻進行數(shù)據(jù)查詢.Ready/Busy:字節(jié)編程地進度可通過Ready/Busy輸出信號檢測，編程期 間,ALE變?yōu)楦唠娖?H后P3.4 （Ready/Busy）端被拉低，表示正在 編程狀態(tài)（忙狀態(tài)）.編程完成后,P3.4變?yōu)楦唠娖奖硎緶?zhǔn)備就緒狀 態(tài).程序校驗：如果加密位LB.LB2沒有進行編程，則代碼數(shù)據(jù)可通 過地址和數(shù)據(jù)線讀回原編寫地數(shù)據(jù)，采用下圖地電路，程序

15、存儲器地 地址由P1 口和P2 口地P2.0 P2.3輸入，數(shù)據(jù)由P0 口讀個人收集整理資料，僅供交流學(xué)習(xí)，勿作商業(yè)用途出，P206.P2.7 和P3.6.P3.7 地控制信號見表6,PSEN保持低電平,ALE.EA和RST保持高電平.校驗時,P0 口必須接上10k左右地上拉電阻.ADOOOOH/OFI FHSEE FLASHiPROiGiRAMMlNG MODES TABLEa-24 MHZP1F2 O -F2.3 ROP2 GP2 .7ALEP3 6P3.7XTAJ-ZEAXTAL1IRSTONOPSENA7Al 1DATA圖2-1-1編程電路ADDR.OOOOH/OFFTHA8A11A7

16、POPGM DATA (USE 10K PULLUPS)SEE FLASHPROGRAMMI NGMODES TABLE3-24 MHzP2 7X1AL2X1AL1GNDALEEARSTPSEN圖2-2-2 校驗電路2.2芯片擦除：利用控制信號地正確組合（表6）并保持ALE/PROCSI腳10ms地低 電平脈沖寬度即可將EPROM車列（4k字節(jié)）和三個加密位整片擦除， 代碼陣列在片擦除操作中將任何非空單元寫入“1，這步驟需在編程之前進行.個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途讀片內(nèi)簽名字節(jié)：89C51單片機內(nèi)有3個簽名字節(jié)，地址為030H.031H和032H.于 聲明該器件地廠商.號和編

17、程電壓.讀簽名字節(jié)地過程和單元 030H.031H和032H正常校驗相仿，只需要將P3.6和P3.7保持低電 平,返回值意義如下：(030H) = 1EH 聲明產(chǎn)品由ATMEL公司制造.(031H) = 51H 聲明為89C51單片機.(032H) = FFH 聲明為12V編程電壓.(032H) = 05H 聲明為5編程電壓.編程接口：采用控制信號地正確組合可對 Flash閃速存儲陣列中地每一代 碼字節(jié)進行寫入和存儲器地整片擦除，寫操作周期是自身定時地，初 始化后它將自動定時到操作完成.微機接口實現(xiàn)兩種信息形式地交換 在計算機之外，由電子系統(tǒng)所處理地信息以一種物理信號形式存在，但在程序中，它是

18、用數(shù)字表示地.任一接口地功能都可分為以某種形 式進行數(shù)據(jù)庫變換地一些操作，所以外部和內(nèi)部形式地轉(zhuǎn)換是由許多 步驟完成地.模擬-數(shù)字轉(zhuǎn)換器(ADC用來將連續(xù)變化信號變成相應(yīng) 地數(shù)字量，這數(shù)字量可是可能性地二進制數(shù)值中地一固定值.如果傳感器輸出不是連續(xù)變化地，就不需模擬-數(shù)字轉(zhuǎn)換.這種情況下，信號 調(diào)理單元必須將輸入信號變換成為另一信號，也可直接與接口地下一部分，即微計算機本身地輸入輸出單元相連接.輸出接口采用相似地形式，明顯地差別在于信息流地方向相反；是從程序到外部世界.這種個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途情況下，程序可稱為輸出程序，它監(jiān)督接口地操作并完成數(shù)字-模擬轉(zhuǎn) 換器（DAC所

19、需數(shù)字地標(biāo)定.該子程序依次送出信息給輸出器件，產(chǎn) 生相應(yīng)地電信號，由DAC轉(zhuǎn)換成模擬形式.最后，信號經(jīng)調(diào)理（通常是 放大）以形成適應(yīng)于執(zhí)行器操作地形式.在微機電路中使用地信號幾 乎總是太小而不能被直接地連到“外部世界”，因而必須用某種形式將其轉(zhuǎn)換成更適宜地形式.接口電路部分地設(shè)計是使用微機地工程師 所面臨最重要地任務(wù)之一.我們已經(jīng)了解到微機中，信號以離散地位 形式表示.當(dāng)微機要與只有打開或關(guān)閉操作地設(shè)備相連時,這種數(shù)字形式是最有用地，這里每一位都可表示一開關(guān)或執(zhí)行器地狀態(tài).為了解決實際問題，一個單片機不僅包括CPU程序和數(shù)據(jù)存儲器，另外，它 必須含有通過CPU訪問外部信息地硬件.一旦CPU收集

20、到數(shù)據(jù)信息和 流程，它必須能夠改變外部領(lǐng)域地一部分，這些硬件設(shè)備稱作外圍設(shè) 備，它們是CPU通往外部地窗口 .單片機可利用外圍設(shè)備中最基本地用于一般用途地I/O接口，每個I/O接口既可作為輸入端又可作為輸出端，每個I/O接口地功能取 決與程序初始化階段對數(shù)據(jù)方位寄存器相應(yīng)位進行置一和清零操作，通過CPU指令對數(shù)據(jù)寄存器相應(yīng)位進行置一和清零來置一和清零輸 出端口，同樣輸入端口邏輯位也可以通過 CPU指令訪問.一些類型地 串行口單元允許CPU與外部設(shè)備進行串口通信，用串口位代替平行位 進行通信需要少許地I/O 口，這樣使通信費用降低但速度也相對慢些 串口傳送可以同步也可以異步.個人收集整理資料,僅

21、供交流學(xué)習(xí),勿作商業(yè)用途The application and programming algorithm of AT89C511 The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and en

22、hanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing proc

23、ess and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of itsAT89C51 automotive microcontrollers. The goals of

24、 this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction個人收集整理資料,

25、僅供交流學(xué)習(xí),勿作商業(yè)用途with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handl

26、e high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. Th

27、e automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive

28、power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, abilityto service the high numberof time and event driven int

29、egratedperipherals needed in real個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such

30、as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components

31、is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system levelunder worst case environ

32、mental andvoltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of vario

33、us micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途of testing are performed on the device.The AT89C51 provides the following standard features:4Kby

34、tes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two softw

35、are selectable power saving modes. The Idle Modestops the CPUwhile allowing the RAM,timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAMcontents but freezes the oscillator disabling allother chip functions until the next hardware reset.-料-J-11

36、 口MT a EUHJWHH | mHT 3! lOmrUVHB：TRI0一上昌Figure 1-2-1Block DiagramAkin TiU H K. OTZKH.中 IWLRJ TPin DescriptionVCC Supply voltage.個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途GND Ground.Port 0 : Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When1s are written t

37、o port 0 pins, the pins can be used as high impedance inputs .Port 0 may also be configured tobe themultiplexed low order address/data bus during accesses to external program and data memory. In this modeP0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outpu

38、ts the code bytes during program verification. External pullups are required during program verification.Port 1 : Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by th

39、e internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2 : Port 2 is an 8-bit bi-directional I

40、/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I

41、IL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during

42、 fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVXDPTR)n this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2

43、 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3 : Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written t

44、o Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special feature個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途soft the AT89C51 as list

45、ed below:RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash p

46、rogramming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALEpulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bi

47、t 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVXor MOVCinstruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEIN Program Store Enable is the read strobe to external program me

48、mory. WhentheAT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSENactivations are skipped during each access to external data memory.EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch cod

49、e from external個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EAwill be internally latched on reset. EA should be strapped to VCC for internalprogram executions. This pin all receives the 12-volt programming enable volta

50、ge (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1： Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respecti

51、vely, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shownin Figure 1. Either a quarts crystal or ceramic resonator may be used.To drive the device from an external clock source, XTAL2should be left unconnected while XTAL1 is driven as shown in Figure2.There a

52、re no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimumand maximum voltage high and low time specificationsmust beobserved. Idle ModeIn idle mode, the CPUputs itselfto sleepwhile all the o

53、n chip peripherals remain active. The mode isinvoked by software. The content of the on-chip RAMand all the個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that whe

54、n idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAMin this event, but access to the port pins is not inhibited. T

55、o eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instructi

56、on that invokes power-down is the last instruction executed. The on-chip RAMand Special Function Registers retain their values until the power-down modeis terminated. The only exit from power-down is a hardware reset. Reset redefines the SFR but does not change the on-chip RAM. The reset should not

57、be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The AT89C51 code memory個人收集整理資料,僅供交流學(xué)習(xí),勿作商業(yè)用途array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chi

58、p Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following

59、 steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPPto 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or t

60、he lock bits.The byte-write cycle isself-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51features Data Polling to indicate the end of a write cycle. Du