數(shù)字設(shè)計 第6章 組合邏輯設(shè)計實踐

Chapter6CombinationalLogicDesignPracticesMSIbuildingblocksaretheimportantelementofcombinationalcircuits.4/21/20231.本章重點具備一定功能的通用組合邏輯電路的設(shè)計方法及實例掌握常用的MSI的使用方法及功能擴展掌握譯碼器、MUX實現(xiàn)組合邏輯功能的方法能分析、設(shè)計由MSI構(gòu)建的電路4/21/20232.6.1DocumentationStandard1.SignalNamesandActiveLevelsMostsignals(signalname)haveactivelevel.

activehighactivelowNamingconventionsurffix“_L”attachingtosignalnamerepresentactivelowlevel.Like,EN_L、READY_L……Inlogicrelation,EN_L=EN’，READY_L=READY’。4/21/20233.2.ActivelevelsforpinsENEN_LDinstartDoutflgstart_LDinDoutflg_LInversionbubbleActivelowENENDinstartDoutflgstartDinDoutflgActivehign4/21/20234.Exp2：①EN=1(activehigh),datacanbetransferred②EN=0(activelow),datacanbetransferredENCLKEN_LCLK4/21/20235.3.bubble-to-bubblelogicdesignMakethelogiccircuiteasiertounderstand.Exp：NotmatchABSELDATAABASELDATAmatch4/21/20236.6.3CombinationalPLDs1.Programmablelogicarrays(PLA)twolevel“AND—OR”device.Canbeprogrammedtorealizeanysum-of-productslogicexpression.Ann×mPLAwithpproductterms:n—inputsm—outputsp—productterms4/21/20237.4×3with6producttermsANDarrayORarray4/21/20238.4/21/20239.2.ProgrammableArrayLogicDevicesFixedORarray，programmableANDarrayBidirectionalinput/outputpins，熔絲型PAL16L8，Outputenable4/21/202310.3.GenericArrayLogicDevices（GAL）aninnovationofthePAL;canbeerasedandreprogrammed;4/21/202311.6.4DecoderAnimportanttypeofcombinationalcircuit.inputcodeword

enableinputOutputcodeword

decodeer1-to-1mapping1-out-of-mcoden<mn-bitm-bit4/21/202312.1、bianrydecodersinputcode：n-bitoutputcode：2n-bit⑴2-4decoder（2-22）

I1I0Y3Y2Y1Y0truthtable：？Yi：？I1I0Y3Y2Y1Y0000001010010100100111000Yi=miY0=I1’·I0’ Y1=I1’·I0Y2=I1·I0’ Y3=I1·I02-4decoderOneinputcombinationchoosesanoutputport.4/21/202313.2-4decoderwithenableinputYi=EN·miENI1I0Y3Y2Y1Y00××00001000001101001011001001111000I1I0Y3Y2Y1Y0EN2-4decoder4/21/202314.（2）74×139,dual2-4decoderInputcode：B（MSB）A（LSB）Alsobecalledaddressinput.Outputcode：Y3_L~Y0_LEN4/21/202315.（3）74××138,3-8decoderEnableinputEN=G1·G2A_L’·G2B_L’Inputcode：C（MSB）、B、AOutputcode：

Y0_L~Y7_LYi_L=（EN·mi）’Y0_LY1_LY2_LY3_LY4_LY5_LY6_LY7_LG1G2A_LG2B_LEN4/21/202316.ENmsblsb4/21/202317.2、realizingcombinationalcircuitswithdecoderreview：canonicalsumDecoderoutput：Yi_L=(EN·mi)’whenEN=1，Yi_L=mi’=MiaddanNANDgatetothedecoder’soutput.Exp:(1)F=∑AB（0、3）F=A’·B’+A·BEnableasserted4/21/202318.（2）ifa3-bitnumberXYZisoddnumber，thenODDoutput1，elseoutput0.realizethefunctionwithdecoderandgates.solution：F=？F=ΣXYZ（1，3，5，7）4/21/202319.（3）F=∏XYZ（0、1、5）解：4/21/202320.3.CascadingbinarydecodersHowtoconstructa4-16、5-32……decoder？usemultiple2-4or3-8decoderstocascade.PS.：confirmthenumberofdecodersaccordingtotheinputandoutputbits.onlyonechipworksineachdecodingoperation.4/21/202321.Exp：a4-16decoderInputs:4-bitN3、N2、N1、N0。Outputs:16-bitDEC15_L~DEC0_LNeed23-8decoders.

UsetheMSBoftheinputsaschip-selectbit. 0000

0001 0111… 1000

1001… 1111N3N2N1N0N3N2N1N04/21/202322.Chipselecting4/21/202323.Exp：4-bitprime-numberdetector.Realizingitwith74×138andsomegates.N3N2N1N0F4/21/202324.4、7-segmentdecoderClassifyof7-segdisplayer：inmaterials:LED（發(fā)光二極管）LCD（液晶）Inworkingmode:common-cathode(共陰極)common-anode(共陽極)afbcegddpabcdedpfggndgnd4/21/202325.7-segmentdecodertransformtheinputBCDcodeto7-segmentdisplayingcode.devices：

7446A、74LS47（驅(qū)動共陽）

74LS48、74LS49（驅(qū)動共陰）0000~1001areusefulinputcodes.1010~1111areunusedBCDcode.4/21/202326.74LS494/21/202327.5、BCDdecoder（二—十進制譯碼器）Inputs:BCDY0Y9……BCDdecoderOutput:1-out-of10code74HC424/21/202328.5.5Encoder1、binaryencoder…………inputs:1-out-of-2n

codeI0I1Im(m=2n-1)……output:n-bitY0Y1Yn-1binaryencoder4/21/202329.8-3encoderinputoutputI7I6I5I4I3I2I1I0Y2Y1Y01000000011101000000110001000001010001000010000001000011000001000100000001000100000001000In/out:activehigh4/21/202330.Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7Eachinputporthasitscorrespondingoutputcode.4/21/202331.2、PriorityEncoderifmultipleinputsareasserted,howtodealwith?solution：assignprioritytoeachinputfromhightolow.letI7—highestpriorityanddecreasefromI6downtoI0A2,A1,A0—encodeoutputIDLE—whennoinputisasserted,IDLE=14/21/202332.inputoutputI7I6I5I4I3I2I1I0A2A1A0IDLE1×××××××111001××××××1100001×××××10100001××××100000001×××0110000001××01000000001×00100000000100000000000000014/21/202333.LogicexpressionsforpriorityencoderH7=I7H6=I6·I7’H5=I5·I6’·I7’……H0=I0·I1’·I2’·I3’·I4’·I5’·I6’·I7’A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7IDLE=(I0+I1+I2+I3+I4+I5+I6+I7)’=I0’·I1’·I2’·I3’·I4’·I5’·I6’·I7’ExpressionsforeachassertedinputinthetruthtableofpriorityencoderOutputcodeexpressions4/21/202334.3、74××148PriorityEncoderEI_L：EnableInput.I7_L~I0_L：encodeinput，I7_Lhashighestpriority.A2_L~A0_L：encodeoutputGS_L：GS_L=0whenoneormoreoftherequestinputsareasserted.EO_L：enableoutput,EO_L=0whenalloftherequestinputsarenegativeandEI_L=0.高低優(yōu)先級4/21/202335.74××148真值表4/21/202336.4、cascadingpriorityencoderproblem：howtoconstruct16-4、32-5……priorityencoder？Connectingmultiple8-3endoder.note：makesuretheneedednumberofchipsaccordingtotheinputs.needtoredesigntheoutputcircuitthatcouldproducethecorrectencodingoutput.4/21/202337.16-4priorityencoder:usetwo74××148U1、U2，(1)U1:inputE15_L~E8_L;U2:inputE7_L~E0_L;E15_Listhehighestpriority,(2)output:A3_L~A0_L，activelow;(3)Whenoneormoreinputsisasserted，GS0_L=0；andA3_L~A0_L=1111.4/21/202338.16-4priorityencoderU174HC148A09A110A211GS14D34D45D56D23D12D78D67EI12EO13U274HC148A09A110A211GS14D34D45D56D23D12D01D78D67EI12EO13U3A74HC08U3B74HC08U3C74HC08U3D74HC08D01EN15_LEN14_LEN13_LEN12_LEN11_LEN10_LEN9_LEN8_LEN7_LEN6_LEN5_LEN4_LEN3_LEN2_LEN1_LEN0_LD0_LD1_LD2_LD3_LGS_L4/21/202339.思考：若需要編碼輸出、GS0為高電平有效，如何修改電路輸出結(jié)構(gòu)？P.413figure6-49showsthe32-5priorityencoder’sstrcture,.4/21/202340.6.6Three-stateDevices1、three-statebuffers4/21/202341.EN_LAOUTENEN_LAAOUT_LOUT_LEnablemeans:thebufferoutputnormallogic0、1whenENisasserted；thebufferoutputHi-ZwhenENisnegated.4/21/202342.Applicationdata返回時序addressofdatasource4/21/202343.IssuesinapplicationTPLZ、TPHZ：timethattakesfromnormallogicintoHi-Z;TPZL、TPZH

：timethattakesfromHi-Zintonormallogic;generally，TPLZ、TPHZ<TPZL、TPZH

Buttoconfirmthecorrectioninapplication,acontrollogicisadopted.4/21/202344.74××

138的相關(guān)引腳信號查看電路

截止時間

（停滯時間）4/21/202345.課堂練習(xí)試設(shè)計一個電路，當(dāng)控制信號M=1時，電路為“判一致”電路，即當(dāng)三個輸入變量取值全部相同時輸入為1；當(dāng)控制信號M=0時，電路為“多數(shù)表決”電路，即輸出等于輸入變量中占多數(shù)的取值。請寫出最簡表達式。（注：至少要寫出卡諾圖，三變量為X、Y、Z）4/21/202346.6.7Multiplexer2-to-1MUXABSELYY=SEL’·A+SEL·BS=0，Y=AS=1，Y=BABS=0Y=AABS=1Y=BLogiccircuit4/21/202347.又稱數(shù)據(jù)選擇器，簡稱MUXOutput:enableselect

ndatasource

dataoutput

n≤2s

mj：SEL[j]minterm1、基本結(jié)構(gòu)：4/21/202348.Letb=1,D0D1DjDn-1SELENY……4/21/202349.Exp:4-to-1MUXABCDS1S001101234outputCS0S1output00A01B10C11D4/21/202350.2、MSIMUX（1）8-to-1MUX，74××151EN_LaddressY_LY4/21/202351.返回4/21/202352.G_L

S（2）4-bit,2inputMUX，74××1574/21/202353.（3）2bit,4inputMUX，74××153inputoutput1G_L2G_LBA1Y2Y00001C02C000011C12C100101C22C200111C32C301001C0001011C1001101C2001111C30100002C0100102C1101002C2101102C311××001G_L2G_L4/21/202354.3、ExpandingMUXsExp1：use74××151torealizea16-to-1MUX,somegatescanbeusedifnecessary.Chipsneeded：accordingtothe16inputs,274××151chips.output：combinetwochip’soutputsintooneoutput.4/21/202355.TheMSB(A3)ofinputactasthechip-selectbit.4/21/202356.Exp2：用74××153實現(xiàn)4輸入，4位MUX，。設(shè)4路輸入分別是：1D[3..0]、2D[3..0]、3D[3..0]、4D[3..0]；4位輸出是：Dout[3..0]輸入選擇：S1、S0解：無需外加門，只需要合理安排輸入、輸出數(shù)據(jù)端口即可。4/21/202357.Dout3S1S04/21/202358.4、用MUX實現(xiàn)組合邏輯函數(shù)的標(biāo)準(zhǔn)和

multipleinput,1bitMUX,theoutput：whenENisasserted：thecanonicalsumform.74×151的內(nèi)部電路mj:mintermoftheselect(address)inputs.4/21/202359.MUX的數(shù)據(jù)輸入端與真值表的每行輸出對應(yīng)，MUX的地址選擇端作為最小項產(chǎn)生器，即

真值表：輸出值 輸入變量

MUX：數(shù)據(jù)輸入端 地址端Exp1：acircuitoutput1whenits3-bitinputcanbedividedby3.constructthecircuitbyusing74××151.So：F=∑XYZ（？）

andcircuit？按最小項編號順序變量與選擇端對應(yīng)4/21/202360.例1的電路XYZFU1~W6D04D13D22D31D415D514D613D712S011S29S110Y5~G7VCCGNDR14/21/202361.例2：若例1中輸入數(shù)為4位二進制數(shù)，如何實現(xiàn)？解1：用16輸入，1位的MUX來實現(xiàn)，選用74××150。F=∑WXYZ（0，3，6，9，12，15）解2：仍選用74××151，先對所求函數(shù)的卡諾圖做降維處理。預(yù)備知識：卡諾圖的降維用一個n變量的卡諾圖來處理m變量的函數(shù)（n<m），這種卡諾圖被稱為降維（降次）的卡諾圖。它允許單元格中除了0、1、無關(guān)項外，還可包含單變量或邏輯表達式。4/21/202362.卡諾圖的降維卡諾圖降次的過程：設(shè)m=n+1，在m-變量函數(shù)F(X1,X2,…,Xn,Xn+1)中選擇一個“入圖”的變量Xi，用剩下的n個變量構(gòu)造n-變量卡諾圖。原圖中變量Xi取值相反所覆蓋的相鄰的兩個單元格被合并。（這兩個單元格的其余變量是相同的；在真值表中對應(yīng)著兩行，只有Xi是不同的，其余變量均相同。）00011110FWXYZ000111WYZX10選擇入圖將被合并4/21/202363.降維的基本步驟①先建新的真值表，表中的輸入變量是除Xi而外剩下的變量，新行號由他們的組合值（最小項）確定。②若在原(n+1)變量真值表中，被合并的兩行的入圖變量Xi與對應(yīng)的F取值相同，則新表中F=XiWXYZFFnew×××00Z×××11W、X、Y取值相同4/21/202364.③若在原(n+1)變量真值表中，被合并的兩行的入圖變量Xi與對應(yīng)的F取值相反，則新表中F=Xi’④若在原(n+1)變量真值表中，被合并的兩行的入圖變量Xi所對應(yīng)的F=1，則新表中F=1⑤若在原(n+1)變量真值表中，被合并的兩行的入圖變量Xi所對應(yīng)的F=0，則新表中F=0⑥得新的n變量卡諾圖⑦用MUX實現(xiàn)4/21/202365.輸入輸出WXYZF0000100010001000011101000010100110101110輸入輸出WXYZF1000010011101001011011001110101110011111新輸出FZ’Z0Z’0123新編號4567新編號新輸出FZ0Z’Z4/21/202366.卡諾圖中降維原4變量卡諾圖 新3變量卡諾圖1000010100011110F00100101WXYZ000111WYZX100ZZ’ZZZ’0Z’WXFnewYWYX4/21/202367.例2的電路圖U1~W6D04D13D22D31D415D514D613D712S011S29S110Y5~G7GNDIO1U2AZZ’WXYF4/21/202368.5.Multiplexers、DemultiplexersandBusesdemultiplexersDin……

2nbitparalleloutputdemultiplexers…1-bitD0D1Dm最多m=2nSELn-bitNoDeMUXchips,abinarydecoderwithenableinputcanbeusedasaDeMUX.4/21/202369.MUX、DeMUX應(yīng)用于數(shù)據(jù)的選擇與分配MUX：combinemparallel-inputdatasourcesintoserialoutputdata.DeMUX：routethebusdatato1ofmdestinations.MUXDe

-MUX……SRCASRCBSRCCSRCZSRCSELBUSDSTSELDSTADSTBDSTCDSTZ4/21/202370.（1）MUX：parallel—serialconversion

8-to-1

MUXD0D1D2D3D4D5D6D7S2S1S0t4/21/202371.4/21/202372.（2）DeMUX:serial—parallelconversionUsea74××138asaDeMUX.4/21/202373.DiagramofExp.S2S1S0111110101100011010001000010101014/21/202374.6.8Exclusive-ORgatesandParitycircuits1、XORandXNORgatesXYX⊕Y(X⊕Y)’XORXNOR0001011010101101（X⊙Y）XORXNOR記憶：異或門—相同為0，相異為1異或非門—與異或相反4/21/202375.PropertiesX⊕0=X

X⊕1=X’X⊕X=0

X⊕X’=1X⊕Y=Y⊕XX⊕Y⊕Z=(X⊕Y)⊕Z=X⊕(Y⊕Z)Equivalentsymbols

Anytwosignals(inputsoroutputs)ofanXORorXNORgatemaybecomplementedwithoutchangingtheresultinglogicfunction.4/21/202376.FeatureofXORexpression(k-map)X⊕Y⊕Z=X’YZ’+XY’Z’+X’Y’Z+XYZFXYZ0

1

01101000011110XY01Z010100001111XYZ4/21/202377.2、paritycircuitsCascadenXORgatestoforman+1inputsodd-paritycircuit.Itmeansthatitsoutput1ifanoddnumberofitsinputsare1.ODD=I1⊕I2⊕……⊕In

Daisy-chainconnection4/21/202378.Complementtheoutputofodd-paritycircuit，itcanworksasanEven-paritywhichoutput1ifanevennumberofitsinputare1.Treestructure，hasfasteroperationspeed.4/21/202379.奇偶校驗的實現(xiàn)奇偶校驗碼(補充)由n位信息位+1位奇偶校驗位(paritybit)構(gòu)成。偶校驗編碼：n位信息碼中包含奇數(shù)個1，則偶校驗位(evenparitybit)置為1，使總的1的個數(shù)是偶數(shù)個。奇校驗編碼：n位信息碼中包含偶數(shù)個1，則奇校驗位(oddparitybit)置為1，使總的1的個數(shù)是奇數(shù)個。4/21/202380.Exp：someacircuitadaptoddparity,ifinputdatais3-bit,pleasegivetheparity-bitgenerator.B200001111B100110011B001010101P10010110inputoutput4/21/202381.3、74×2809-bitparitygeneratorGeneratetheparitybitwhenacodewordisstoredortransmitted.Checktheparitybitwhenacodewordisretrievedorreceived.EVEN=A⊕B⊕C⊕D⊕E⊕F⊕(G⊕H⊕I)’ODD=A⊕B⊕C⊕D⊕E⊕F⊕G⊕H⊕I4/21/202382.1databufferdataPINmemoryWRRDRDWRPOUTERROR0101ODD=A⊕B⊕C⊕D⊕E⊕F⊕G⊕H⊕I=PIN=POUT2EN4/21/202383.6.9Comparatorscomparator—comparestwobinarynumberandindicateswhethertheyareequal.Magnitudecomparator—interpretthebinarynumberassignedorunsignednumbersandalsoindicateanarithmeticrelationship(greateroflessthan).4/21/202384.1、structureofcomparator（1）1-bitcomparator（2）multiple-bitcomparatorparallelcomparatoriterativecomparatorDIFF=A0⊕B0EQ=（A0⊕B0）’4/21/202385.Parallelcomparator4-bitparallelcomparatorIterativecomparator(serialcomparator)4/21/202386.2.IterativeCircuitCascadenidenticalmodulesboundaryoutputCICOPIPOC0C1PI0PO0CICOPIPOPI1PO1CICOPIPOPIn-1POn-1CnC2…Cn-1boundaryinputscascadinginputcascadingoutput4/21/202387.comparatormoduleiterativecomparatorEQIEQOXY1X0Y0EQIEQOXYX1Y1EQ1EQ2…EQIEQOXYXn-1Yn-1EQnlowerspeed,butbeeasytoexpand4/21/202388.3.Magnitudecomparators（1）1-bitmagnitudecomparatorsABF(A>B)F(A=B)F(A<B)00010010011010011010FA>B=AB’FA<B=A’BFA=B=A’B’+ABABFA>BFA<BFA=B4/21/202389.（2）multiple-bitMagnitudecomparators2-bit，inputA[1..0]、B[1..0]A1B1A0B0FA>BFA=BFA<B01××110××100001000110010100111110011101111101111114/21/202390.

FA>B=(A1>B1)+(A1=B1)·(A0>B0)

=A1·B1’+(A’B’+AB)·(A1·B1’)FA=B=(A1=B1)·(A0=B0)FA<B=(A1<B1)+(A1=B1)·(A0<B0)A1B1A0B0FA>BFA=BFA<BA1<B1××1A1>B1××1A1=B1A0<B01A1=B1A0>B01A1=B1A0=B01Pseudo-logic4/21/202391.4.StandardMSImagnitudecomparator74×85:4-bitMagnitudeinput:A[3..0],B[3..0]Cascadinginput：ALBI、AEBI、AGBI，whichareusedtoexpandingcomparator.output：ALBO、AEBO、AGBOAGBO=(A>B)+(A=B)·AGBIAEBO=(A=B)·AEBIALBO=(A<B)+(A=B)·ALBI4/21/202392.Cascadingmagnitudecomparatorinserialmode:iterativecomparatorFA>BFA=BFA<B4/21/202393.inparallelmodeFA>BFA=BFA<BX[11..8]Y[11..8]X[7..4]Y[7..4]X[3..0]Y[3..0]4/21/202394.ClassexerciseABCDFD’AA’DC’D’C’ABJudgewhetherthefollowingcircuithasstatichazardornot,ifstatichazardexist,pleasepointitandeliminatebyusingK-map.Thenwritethehazardlessminimalsum.4/21/202395.6.10Adders、SubtractorsandA