時(shí)序電路-06C(時(shí)序電路VHDL設(shè)計(jì)典型實(shí)例)

數(shù)字電路與邏輯設(shè)計(jì)二、常用時(shí)序邏輯電路設(shè)計(jì)（1）觸發(fā)器設(shè)計(jì)（D、JK）（2）計(jì)數(shù)器設(shè)計(jì)（分頻器）（3）移位寄存器設(shè)計(jì)（4）狀態(tài)機(jī)設(shè)計(jì)：序列檢測(cè)器

Process的物理意義Process進(jìn)程

由敏感信號(hào)觸發(fā)，并以Process結(jié)束為時(shí)間分界點(diǎn)，實(shí)現(xiàn)信號(hào)的初態(tài)到次態(tài)的轉(zhuǎn)換。分界點(diǎn)以前引用信號(hào)的當(dāng)前值（初態(tài)值），并通過(guò)賦值語(yǔ)句指定信號(hào)的次態(tài)值；分界點(diǎn)以后，次態(tài)值生效。時(shí)序電路VHDL描述方法狀態(tài)方程法

確定敏感信號(hào)，用信號(hào)初態(tài)值和其他輸入表示出次態(tài)值，然后代入賦值語(yǔ)句。狀態(tài)表法確定敏感信號(hào)，按一定規(guī)則列出狀態(tài)轉(zhuǎn)換表，逐行描述或多行概括描述。（1）觸發(fā)器設(shè)計(jì)DQCLKCLKDQn+1無(wú)變化XQn0->1000->111D觸發(fā)器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYdffISPORT(clk,d:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDdff;ARCHITECTUREaOFdffISBEGINprocess(clk)beginif(clk'eventandclk='1')thenq<=d;endif;endprocess;ENDa;狀態(tài)方程：

J-K觸發(fā)器特性表JKQn+1功能說(shuō)明00011011Qn01Qn不變置0置1翻轉(zhuǎn)JK觸發(fā)器cpCLKI.依據(jù)狀態(tài)方程實(shí)現(xiàn)JK觸發(fā)器Libraryieee;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;entityjkjkisport(j,k,clk:instd_logic;Q,nQ:bufferstd_logic);endjkjk;buffer端口模式：端口既作為實(shí)體的輸出，又回到實(shí)體內(nèi)部做驅(qū)動(dòng)信號(hào)。architecturebhofjkjkisbegin

process(clk)

begin

if(clk'eventandclk='0')thenQ<=(jand(notQ))OR((notk)andQ);nQ<=not((jand(notq))OR((notk)andq));

endif;

end

process;endbh;II.依據(jù)狀態(tài)轉(zhuǎn)換表實(shí)現(xiàn)JK觸發(fā)器Libraryieee;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;entityjkjkisport(j,k,clk:instd_logic;Q,nQ:bufferstd_logic);endjkjk;architecturebh2ofjkjk1isbegin

process(clk)

begin

if(clk'eventandclk='0')then

ifj='0'andk='1'thenq<='0';nq<='1';

elsifj='1'andk='0'thenq<='1';nq<='0';

elsifj='0'andk='0'thenq<=q;nq<=nq;

elsifj='1'andk='1'thenq<=notq;nq<=notnq;

endif;

endif;

endprocess;endbh2;(2)-A簡(jiǎn)單計(jì)數(shù)器設(shè)計(jì)計(jì)數(shù)器CLKQ3Q2Q1Q0四位加計(jì)數(shù)器LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk:inSTD_LOGIC;q:buffer

STD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk)

begin

if(clk'eventandclk='1')thenq<=q+1;

endif;

endprocess;ENDa;四位加計(jì)數(shù)器計(jì)數(shù)器CLKCLR(2)-B帶同步清零、同步置數(shù)功能的計(jì)數(shù)器LDQ3Q2Q1Q0D3D2D1D0控制信號(hào)CLR、LD：具有更高優(yōu)先級(jí)LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk,clr,ld:inSTD_LOGIC;d:inSTD_LOGIC_vector(3downto0);q:bufferSTD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk)

begin

if(clk'eventandclk='1')thenif(clr='1')then

q<="0000";elsif(ld='1')thenq<=d;

elseq<=q+1;

endif;endif;endprocess;ENDa;計(jì)數(shù)器CLKCLR(2)-C帶異步清零、同步置數(shù)功能的計(jì)數(shù)器LDQ3Q2Q1Q0D3D2D1D0LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk,clr,ld:inSTD_LOGIC;d:inSTD_LOGIC_vector(3downto0);q:bufferSTD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk,clr)begin

if(clr=‘1’)thenq<=“0000”;

elsif(clk'eventandclk='1'andld=‘1’)

then

q<=d;elsif(clk'eventandclk='1'andld=‘0’)

then

q<=q+1;endif;

endprocess;ENDa;process(clk,clr)begin

if(clr=‘1’)thenq<=“0000”;

else--即clr=‘0’

if(clk'eventandclk='1')

thenif(ld='1')then

q<=d;

elseq<=q+1;

endif;

endif;endif;

endprocess;ENDa;(2)-D帶進(jìn)位計(jì)數(shù)器設(shè)計(jì)計(jì)數(shù)器CLKQ3Q2Q1Q0四位加計(jì)數(shù)器COUTLIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk:inSTD_LOGIC;q:buffer

STD_LOGIC_vector(3downto0);cout:outstd_logic);ENDcounter;ARCHITECTUREaOFcounterISBEGINARCHITECTUREbOFcounterISBEGINprocess(clk)begin

if(clk'eventandclk='1')thenq<=q+1;

endif;endprocess;cout<=‘1’whenq=15else‘0’;ENDb;進(jìn)程設(shè)計(jì)狀態(tài)轉(zhuǎn)換并列語(yǔ)句實(shí)現(xiàn)輸出計(jì)數(shù)器CLKQ3Q2Q1Q0帶進(jìn)位的十進(jìn)制加計(jì)數(shù)器COUTARCHITECTUREbOFcounterISBEGINprocess(clk)begin

if(clk'eventandclk='1')then

if(q<9)thenq<=q+1;

elsif

q>=9q<=“0000”;

endif;

endif;endprocess;cout<=‘1’whenq=9else‘0’;ENDb;進(jìn)程設(shè)計(jì)狀態(tài)轉(zhuǎn)換并列語(yǔ)句實(shí)現(xiàn)輸出(2)-E分頻器Tclk=1usTcout=10us計(jì)數(shù)器就是對(duì)時(shí)鐘脈沖計(jì)數(shù)，同時(shí)計(jì)數(shù)器還是一個(gè)分頻器。fclk=1x106Hzfcout=1x105Hz（3）移位寄存器設(shè)計(jì)4位右移移位寄存器Reset:異步清零右移移位寄存器dinresetclkQAQBQCQDlibraryieee;useieee.std_logic_1164.all;ENTITYshifterISPORT(

din:instd_logic;reset,clk:instd_logic;QA,QB,QC,QD:bufferstd_logic);

ENDshifter;ARCHITECTUREbehaveOFshifterISBEGINProcess(reset,clk)Begin

if(reset='1')

then

QA<='0';QB<='0';QC<='0';QD<='0';

else

if

(clk'Eventandclk='1')then

QA<=din;QB<=QA;QC<=QB;QD<=QC;

endif;

endif;endprocess;Endbehave;（4）“狀態(tài)機(jī)”概念及設(shè)計(jì)

我們可以用輸入信號(hào)X和電路狀態(tài)Q來(lái)描述時(shí)序電路的邏輯功能，這時(shí)時(shí)序電路稱為

狀態(tài)機(jī)（StateMachine）。根據(jù)輸出信號(hào)和輸入信號(hào)以及電路狀態(tài)的關(guān)系，狀態(tài)機(jī)可以分為兩種：穆爾（Moore）型和米利（Mealy）型。Y=F[X,Q]

Y=F[Q]

米利（Mealy）型：穆爾（Moore）型：典型狀態(tài)機(jī)示例—序列信號(hào)檢測(cè)器目標(biāo)序列信號(hào)：“110”序列檢測(cè)器CLKZdin序列信號(hào)檢測(cè)器工作波形圖S0S20/01/0S11/00/10/01/0Mealy型序列信號(hào)檢測(cè)器—狀態(tài)圖序列信號(hào)：110Sdin/Z‘1’‘11’S0/0S2/001S1/0101Moore型序列信號(hào)檢測(cè)器—狀態(tài)圖序列信號(hào)：110S/Zdin‘1’‘11’S3/1‘110’001LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYsqsISPORT(din,clk:inStd_logic;z:outStd_logic);ENDsqs;Mealy型-VHDL代碼轉(zhuǎn)換ARCHITECTUREaOF

sqsISTYPESTATE_TYPEIS(s0,s1,s2);SIGNALstate:STATE_TYPE;BEGIN

Mealy型-VHDL代碼轉(zhuǎn)換PROCESS(clk) BEGIN

If

（clk’EVENTANDclk=‘1’）thenCASEstateIS

WHENs0=>IFdin=‘1’

THENstate<=s1;

elsestate<=s0; ENDIF;

WHENs1=>IFdin=‘1'THENstate<=s2;

elsestate<=s0; ENDIF;

WHENs2=>IFdin='0'THENstate<=s0;

elsestate<=s2; ENDIF;

WHENothers=> state<=s0; ENDCASE;Endif;

ENDPROCESS;z<='1'when(state=s2anddin=’0’)else'0';

--輸出不僅與狀態(tài)有關(guān)，而且和輸入有關(guān)。ENDa;

Mealy型-VHDL代碼轉(zhuǎn)換序列信號(hào)：110序列檢測(cè)器CLKZdinRst狀態(tài)機(jī)自啟動(dòng)：RST復(fù)位控制LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYsqsISPORT(Rst,din,clk:inStd_logic;z:outStd_logic);ENDsqs;ARCHITECTUREaOFsqsISTYPESTATE_TYPEIS(s0,s1,s2);SIGNALstate:STATE_TYPE;BEGIN

PROCESS(rst,clk) BEGINIf(Rst=‘1’)thenstate<=s0;elsif

（clk‘EVENTANDclk=’1‘）thenCASEstateIS

WHENs0=>IFdin=‘1’

THENstate<=s1;