鍵盤掃描與計(jì)算器VHDL仿真設(shè)計(jì)

./簡(jiǎn)易計(jì)算器設(shè)計(jì)——EDA實(shí)驗(yàn)報(bào)告實(shí)驗(yàn)內(nèi)容實(shí)驗(yàn)要求：完成個(gè)位數(shù)的加減乘運(yùn)算,輸入用矩陣鍵盤,輸出用數(shù)碼管顯示,每輸入一次數(shù)據(jù)要顯示在數(shù)碼管上。矩陣鍵盤共16個(gè)按鍵,用其中10個(gè)做個(gè)位數(shù)的輸入,用3個(gè)分別做加減乘運(yùn)算,用其中1個(gè)做等于操作,各位數(shù)的運(yùn)算結(jié)果最多兩位,用動(dòng)態(tài)掃描數(shù)碼管顯示運(yùn)算結(jié)果。小組成員實(shí)現(xiàn)方法系統(tǒng)組成與連接原理如圖所示,主要由由七個(gè)功能模塊組成：分頻模塊〔為鍵盤掃描模塊和防抖模塊提供時(shí)鐘〕、鍵盤掃描驅(qū)動(dòng)模塊〔依次置零〕、鍵盤按鍵值編碼模塊、鍵盤編碼值防抖模塊、運(yùn)算模塊,數(shù)碼管顯示驅(qū)動(dòng)模塊、動(dòng)態(tài)掃描驅(qū)動(dòng)模塊。分頻鍵值編碼防抖鍵盤分頻鍵值編碼防抖鍵盤矩陣行驅(qū)動(dòng)時(shí)鐘時(shí)鐘數(shù)碼管顯示運(yùn)算數(shù)碼管顯示運(yùn)算數(shù)碼管數(shù)碼管動(dòng)態(tài)顯示動(dòng)態(tài)顯示1.分頻模塊由于FPGA實(shí)驗(yàn)板的原始時(shí)鐘頻率高達(dá)33.8688MHz,所以不能直接接入設(shè)計(jì)模塊中使用,就需要用到分頻模塊。將33.8688MHz分頻到4KHz和10Hz來(lái)使用,一個(gè)用于行驅(qū)動(dòng)掃描時(shí)鐘,一個(gè)用于防抖模塊。所以,采用寫一個(gè)可變分頻元件來(lái)調(diào)用。元件視圖：主要代碼如下〔完整代碼見(jiàn)附錄,下同〕：architectureRTLoffreq_divisioniscomponentfredivnisgeneric<n:positive>;Port<clkin:inSTD_LOGIC;clkout:outSTD_LOGIC>;endcomponent;beginU1:fredivngenericmap<n=>3>portmap<clkin=>clk,clkout=>clkout_kb>;endRTL;仿真結(jié)果如下圖：達(dá)到預(yù)期的目的2.行驅(qū)動(dòng)模塊〔依次對(duì)行置零〕：鍵盤掃描的原理就是檢測(cè)行列信號(hào)然后判斷出具體是按下了哪一個(gè)按鍵。所以,對(duì)行依次置零,當(dāng)置零頻率較快時(shí),按下某一個(gè)按鍵后,一定能得到某一列的信號(hào)輸出為零,如下圖：當(dāng)行信號(hào)為1110時(shí),若按下了0鍵,就會(huì)得到1110的列信號(hào),立馬就快可以譯碼出按鍵值,若按下4鍵、8鍵、C鍵則都不會(huì)有輸出。主要代碼如下： process<clkin> begin ifclr='1'then count<="00"; elsifrising_edge<clkin>then ifcount="11"then count<="00"; else count<=count+1; endif; endif; endprocess; process<count> begin ifcount="01"then keydrv<="1110"; elsifcount="10"then keydrv<="1101"; elsifcount="11"then keydrv<="1011"; elsifcount="00"then keydrv<="0111"; endif; endprocess;仿真結(jié)果如下圖：達(dá)到預(yù)期的目的3.鍵值編碼模塊依據(jù)行驅(qū)動(dòng)模塊,當(dāng)按下某一個(gè)按鍵后,立馬可以根據(jù)行列和并位信號(hào)得到唯一的鍵盤編碼值,用5位矢量來(lái)保存結(jié)果,當(dāng)沒(méi)有按鍵按下時(shí),編碼值一直保持著‘11111’不變,并在后端的模塊中不對(duì)其做任何處理。以下列出部分編碼表〔完整編碼表見(jiàn)附錄〕：十進(jìn)制數(shù)行&列HEX七段碼HEX011101110EE11111107E411011110DE011001133511011101DD10110115B主要代碼如下： process<clk> begin ifclr='0'then ifrising_edge<clk>then iftemp1="11101110"then keyvalue1<="00000"; --0 elsiftemp1="11101101"then keyvalue1<="00001"; --1 elsiftemp1="11101011"then keyvalue1<="00010"; --2 elsiftemp1="11100111"then keyvalue1<="00011"; --3 elsiftemp1="11011110"then keyvalue1<="00100"; --4 elsiftemp1="11011101"then keyvalue1<="00101"; --5 elsiftemp1="11011011"then keyvalue1<="00110"; --6 elsiftemp1="11010111"then keyvalue1<="00111"; --7 elsiftemp1="10111110"then keyvalue1<="01000"; --8 elsiftemp1="10111101"then keyvalue1<="01001"; --9 elsiftemp1="10111011"then keyvalue1<="01010"; --10 elsiftemp1="10110111"then keyvalue1<="01011"; --11 elsiftemp1="01111110"then keyvalue1<="01100"; --12 elsiftemp1="01111101"then keyvalue1<="01101"; --13 elsiftemp1="01111011"then keyvalue1<="01110"; --14 elsiftemp1="01110111"then keyvalue1<="01111"; --15 endif; endif; endif; endprocess;波形仿真如下圖：4.防抖模塊鍵盤按鍵物理模型如下：通常的按鍵所用開(kāi)關(guān)為機(jī)械彈性開(kāi)關(guān),當(dāng)機(jī)械觸點(diǎn)斷開(kāi)、閉合時(shí),由于機(jī)械觸點(diǎn)的彈性作用,一個(gè)按鍵開(kāi)關(guān)在閉合時(shí)不會(huì)馬上穩(wěn)定地接通,在斷開(kāi)時(shí)也不會(huì)一下子斷開(kāi)。因而在閉合與斷開(kāi)的瞬間均伴隨有一連串的抖動(dòng),為了不產(chǎn)生這種現(xiàn)象而作的措施就是按鍵消抖。抖動(dòng)時(shí)間的長(zhǎng)短由按鍵的機(jī)械特性決定,一般為5ms～10ms。一般來(lái)說(shuō),軟件消抖的方法是不斷檢測(cè)按鍵值,直到按鍵值穩(wěn)定。實(shí)現(xiàn)方法：假設(shè)未按鍵時(shí)輸入1,按鍵后輸入為0,抖動(dòng)時(shí)不定?？梢宰鲆韵聶z測(cè)：檢測(cè)到按鍵輸入為0之后,延時(shí)5ms～10ms,再次檢測(cè),如果按鍵還為0,那么就認(rèn)為有按鍵輸入。延時(shí)的5ms～10ms恰好避開(kāi)了抖動(dòng)期。本模塊是采用多次采樣來(lái)達(dá)到防抖的,只有在給定的采樣次數(shù)內(nèi),都保證采樣結(jié)果一致時(shí)才會(huì)輸出按鍵編碼值。主要代碼如下：casecountis when"0000"=>test1<=temp; when"0001"=>test2<=temp; when"0010"=>test3<=temp; when"0011"=>test4<=temp; when"0100"=>test5<=temp; when"0101"=>test6<=temp; when"0110"=>test7<=temp; when"0111"=>test8<=temp; when"1000"=>test9<=temp; when"1001"=>test10<=temp; when"1010"=>test11<=temp; when"1011"=>test12<=temp; when"1100"=>test13<=temp; when"1101"=>test14<=temp; when"1110"=>test15<=temp; when"1111"=>test16<=temp; whenothers=>null; endcase; iftest1=test5andtest2=test6andtest3=test7andtest4=test8andtest5=test9andtest6=test10andtest7=test11andtest8=test12andtest9=test13andtest10=test14andtest11=test15andtest12=test16andtest1/="UUUUUUUU"then仿真波形如下：從圖中可以看出最終temp1從臨時(shí)信號(hào)temp得到最終輸出,達(dá)到防抖：5.運(yùn)算模塊當(dāng)前段的模塊經(jīng)過(guò)防抖處理以后得到穩(wěn)定的按鍵信號(hào),比如1+2=3,轉(zhuǎn)化為編碼值就是11101101101110110111110111100111=>EDBBEB7DE7<具體編碼表見(jiàn)附錄>主要代碼如下： ifysfh=0thenresult<=first+second; elsifysfh=1thenresult<=first-second; elsifysfh=2thenresult<=first*second; endif;n<=n+'1'; elsifn="100"then n<="000"; endif; endif; endprocess; process<n>begin ifn="001"thenkeyvaluein<=conv_std_logic_vector<first,8>; elsifn="011"thenkeyvaluein<=conv_std_logic_vector<second,8>; elsifn="100"thenkeyvaluein<=conv_std_logic_vector<result,8>; endif; endprocess;仿真波形如下：以1+3=4和5x6=30為例：編碼：01+03=0405X06=1E6.數(shù)碼管顯示模塊以與動(dòng)態(tài)掃描模塊由于次兩個(gè)模塊是密切相關(guān)的,所以統(tǒng)一到一起驗(yàn)證。經(jīng)過(guò)運(yùn)算得到最終的顯示結(jié)果后,要在七段數(shù)碼管中顯示,就必須有每一個(gè)數(shù)的七段碼,同時(shí),由于前面的運(yùn)算模塊的結(jié)果最大可以達(dá)到81,也就是需要8位二進(jìn)制,兩位十進(jìn)制來(lái)表示,所以就必須通過(guò)顯示模塊來(lái)分離出十位和個(gè)位。分離出十位和個(gè)位以后,就必須要利用動(dòng)態(tài)掃描使兩個(gè)數(shù)都能顯示出來(lái)。因?yàn)?個(gè)七段數(shù)碼管的abcdefg位是連在一起的,只有利用分時(shí)間隔來(lái)顯示,一次使能一個(gè)數(shù)碼管,顯示一位數(shù),當(dāng)頻率較高時(shí),就可以得到兩位數(shù)的顯示效果。數(shù)碼管顯示模塊主要代碼如下： ifnum=0then ten:=0;one:=10; elsifnum<10andnum>0then ten:=0;one:=num; elsifnum<20andnum>9then ten:=1;one:=num-10; elsifnum<30andnum>19then ten:=2;one:=num-20; elsifnum<40andnum>29then ten:=3;one:=num-30; elsifnum<50andnum>39then ten:=4;one:=num-40; elsifnum<60andnum>49then ten:=5;one:=num-50; elsifnum<70andnum>59then ten:=6;one:=num-60; elsifnum<80andnum>69then ten:=7;one:=num-70; elsifnum<90andnum>79then ten:=8;one:=num-80; elsifnum<100andnum>89then ten:=9;one:=num-90; endif; t<=conv_std_logic_vector<ten,4>; o<=conv_std_logic_vector<one,4>;動(dòng)態(tài)掃描模塊主要代碼如下： ifcount="00"then showout<=show1;en<="00000010"; elsifcount="01"then showout<=show2;en<="00000001"; endif;仿真波形如下：數(shù)碼顯示模塊 Show1是十位數(shù),show2是個(gè)位數(shù),分別為7E<七段碼十六進(jìn)制>和30,即01。掃描顯示模塊數(shù)碼管使能信號(hào)en依次在01和02中變化,翻譯成八段碼就是00000001和00000010模塊調(diào)用將上述模塊按照層次調(diào)用,就可以得到最頂層的文件,完成計(jì)算器的所有要求功能。調(diào)用圖如下：掃描顯示數(shù)碼管顯示運(yùn)算模塊后端處理防抖模塊鍵盤編碼行驅(qū)動(dòng)頂層文件時(shí)鐘掃描顯示數(shù)碼管顯示運(yùn)算模塊后端處理防抖模塊鍵盤編碼行驅(qū)動(dòng)頂層文件時(shí)鐘模塊：分頻鍵盤鍵盤最終的仿真波形如下： 01=>showout01100003002=>showout11011016D03=>showout111100179由以上波形可以看出：01+02=03的計(jì)算完成了?？偨Y(jié)本次EDA設(shè)計(jì)實(shí)踐,完成了從VHDL代碼編寫到硬件實(shí)現(xiàn)的整個(gè)流程,掌握了一些FPGA的相關(guān)概念以與ISE軟件和Active-HDL軟件的使用方法。最重要的就是組員之間的合作,因?yàn)閂HDL程序是模塊化編寫的,所以不同模塊是由不同人來(lái)完成編譯的,要達(dá)到各個(gè)模塊之間能夠良好的銜接通信,就必須有一個(gè)很好的溝通交流,把大家的思路集中起來(lái),一起討論、編寫、調(diào)試程序。[附錄一]完整程序：分頻：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityfredivnis generic<n:integer:=3>;Port<clkin:inSTD_LOGIC;clkout:outSTD_LOGIC>;endfredivn;architectureBehavioraloffredivnissignalclk1:std_logic:='0';signalcounter:integerrange0ton;beginprocess<clkin>beginifrising_edge<clkin>thenifcounter=<n-1>/2thenclk1<=notclk1;counter<=0;elsecounter<=counter+1;endif;endif;endprocess;clkout<=clk1;endBehavioral;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitykeyscanisPort<clr:instd_logic; clkin:inSTD_LOGIC;keydrv:outSTD_LOGIC_VECTOR<3downto0>>;endkeyscan;architecturebehavioralofkeyscanissignalcount:std_logic_vector<1downto0>;begin process<clkin> beginifclr='1'thencount<="00";elsifrising_edge<clkin>then ifcount="11"then count<="00";else count<=count+1; endif;endif;endprocess;process<count>beginifcount="01"thenkeydrv<="1110";elsifcount="10"thenkeydrv<="1101";elsifcount="11"thenkeydrv<="1011";elsifcount="00"thenkeydrv<="0111";endif;endprocess;endbehavioral;鍵值編碼：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitykeydecoderisPort<clkin,clk,clr:instd_logic;keyin:inSTD_LOGIC_VECTOR<3downto0>;keycode:outSTD_LOGIC_VECTOR<4downto0> >;endkeydecoder;architectureRtlofkeydecoderissignaltemp:STD_LOGIC_VECTOR<7downto0>;signalkeydrv1:STD_LOGIC_VECTOR<3downto0>;signalkeyvalue1:STD_LOGIC_VECTOR<4downto0>;signaltemp1:STD_LOGIC_VECTOR<7downto0>;componentkeyscanPort<clkin,clr:inSTD_LOGIC;keydrv:outSTD_LOGIC_VECTOR<3downto0>>;endcomponent;componentfandou1 Port<clkin,clr:inSTD_LOGIC; temp:instd_logic_vector<7downto0>;temp1:outSTD_LOGIC_VECTOR<7downto0>>; endcomponent;begin u1:keyscanportmap<clkin=>clkin,keydrv=>keydrv1,clr=>clr>;temp<=keydrv1&keyin;u2:fandou1portmap<clkin=>clkin,temp=>temp,temp1=>temp1,clr=>clr>; process<clk> begin ifclr='0'then ifrising_edge<clk>then iftemp1="11101110"then keyvalue1<="00000"; elsiftemp1="11101101"then keyvalue1<="00001"; elsiftemp1="11101011"then keyvalue1<="00010"; elsiftemp1="11100111"then keyvalue1<="00011"; elsiftemp1="11011110"then keyvalue1<="00100"; elsiftemp1="11011101"then keyvalue1<="00101"; elsiftemp1="11011011"then keyvalue1<="00110"; elsiftemp1="11010111"then keyvalue1<="00111"; elsiftemp1="10111110"thenkeyvalue1<="01000"; elsiftemp1="10111101"then keyvalue1<="01001"; elsiftemp1="10111011"then keyvalue1<="01010"; elsiftemp1="10110111"then keyvalue1<="01011"; elsiftemp1="01111110"then keyvalue1<="01100"; elsiftemp1="01111101"then keyvalue1<="01101"; elsiftemp1="01111011"then keyvalue1<="01110"; elsiftemp1="01110111"then keyvalue1<="01111"; endif; endif; endif;endprocess;keycode<=keyvalue1;endrtl;防抖：libraryIEEE;useIEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;useieee.numeric_std.all;entityfangdouisport<keycode:instd_logic_vector<4downto0>; keycode1:outstd_logic_vector<4downto0>; start:outstd_logic; clk_f,clr:instd_logic>;endfangdou;architecturefangdouoffangdouissignalcount1:std_logic_vector<2downto0>;signalkey1:std_logic_vector<4downto0>;signalkey2:std_logic_vector<4downto0>;signalkey3:std_logic_vector<4downto0>;signalkey4:std_logic_vector<4downto0>;signalkey5:std_logic_vector<4downto0>;signalkey6:std_logic_vector<4downto0>;signalkey7:std_logic_vector<4downto0>;signalkey8:std_logic_vector<4downto0>;signalstart_1:std_logic;begin process<clk_f> begin ifclr='1'then key1<="00000"; key2<="00001"; key3<="00010"; key4<="00011"; key5<="00100"; key6<="00101"; key7<="00110"; key8<="00111"; count1<="000"; start_1<='1'; else ifrising_edge<clk_f>thenifcount1="111"then count1<="000"; elsecount1<=count1+'1'; endif; endif; endif; casecount1iswhen"000"=>key1<=keycode;when"001"=>key2<=keycode;when"010"=>key3<=keycode;when"011"=>key4<=keycode;when"100"=>key5<=keycode;when"101"=>key6<=keycode;when"110"=>key7<=keycode;when"111"=>key8<=keycode;whenothers=>null;endcase;ifkey1=key2andkey2=key3andkey3=key4andkey4=key5andkey5=key6andkey6=key7andkey7=key8andkey1/="UUUUU"then keycode1<=key1;start_1<='0'after5ns;endif;endprocess;start<=start_1;endfangdou;運(yùn)算：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;useieee.numeric_std.all;entityyunsuanisport<start:instd_logic;keycode1:instd_logic_vector<4downto0>;keyvaluein:outstd_logic_vector<7downto0>>;endyunsuan;architectureBehavioralofyunsuanissignalfirst,second,result,ysfh:integerrange0to99;signaln:std_logic_vector<2downto0>;beginprocess<start,keycode1> begin ifstart='1'then n<="000"; elseifn="000"then ifkeycode1="00001"thenfirst<=1; elsifkeycode1="00010"thenfirst<=2;elsifkeycode1="00011"thenfirst<=3;elsifkeycode1="00100"thenfirst<=4;elsifkeycode1="00101"thenfirst<=5;elsifkeycode1="00110"thenfirst<=6;elsifkeycode1="00111"thenfirst<=7;elsifkeycode1="01000"thenfirst<=8;elsifkeycode1="01001"thenfirst<=9;elsifkeycode1="00000"thenfirst<=0;endif;n<=n+'1';elsifn="001"thenifkeycode1="01010"thenysfh<=0;elsifkeycode1="01011"thenysfh<=1;elsifkeycode1="01100"thenysfh<=2;endif;n<=n+'1';elsifn="010"thenifkeycode1="00001"thensecond<=1;elsifkeycode1="00010"thensecond<=2;elsifkeycode1="00011"thensecond<=3;elsifkeycode1="00100"thensecond<=4;elsifkeycode1="00101"thensecond<=5;elsifkeycode1="00110"thensecond<=6;elsifkeycode1="00111"thensecond<=7;elsifkeycode1="01000"thensecond<=8;elsifkeycode1="01001"thensecond<=9;elsifkeycode1="00000"thensecond<=0;endif;n<=n+'1';elsifn="011"andkeycode1="01101"thenifysfh=0thenresult<=first+second;elsifysfh=1thenresult<=first-second;elsifysfh=2thenresult<=first*second;endif;n<=n+'1';elsifn="100"thenn<="000";endif;endif;endprocess;process<n>beginifn="001"thenkeyvaluein<=conv_std_logic_vector<first,8>;elsifn="011"thenkeyvaluein<=conv_std_logic_vector<second,8>;elsifn="100"thenkeyvaluein<=conv_std_logic_vector<result,8>;endif;endprocess;endBehavioral;數(shù)碼管顯示：libraryIEEE;useIEEE.STD_LOGIC_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityshumaguanxianshiisport<keyvaluein:instd_logic_vector<7downto0>;clk:instd_logic;show1,show2:outstd_logic_vector<6downto0>>;endshumaguanxianshi;architectureshumaguanxianshiofshumaguanxianshiissignalt:std_logic_vector<3downto0>;signalo:std_logic_vector<3downto0>;beginprocess<clk>variablenum:integerrange0to99;variableten,one:integerrange0to15;beginifrising_edge<clk>then num:=conv_integer<keyvaluein>;ifnum=0thenten:=0;one:=10;elsifnum<10andnum>0thenten:=0;one:=num;elsifnum<20andnum>9thenten:=1;one:=num-10;elsifnum<30andnum>19thenten:=2;one:=num-20;elsifnum<40andnum>29thenten:=3;one:=num-30;elsifnum<50andnum>39thenten:=4;one:=num-40;elsifnum<60andnum>49thenten:=5;one:=num-50;elsifnum<70andnum>59thenten:=6;one:=num-60;elsifnum<80andnum>69thenten:=7;one:=num-70;elsifnum<90andnum>79thenten:=8;one:=num-80;elsifnum<100andnum>89thenten:=9;one:=num-90;endif;t<=conv_std_logic_vector<ten,4>; o<=conv_std_logic_vector<one,4>;casetiswhen"0000"=>show1<="0000000";when"0001"=>show1<="0110000";when"0010"=>show1<="1101101";when"0011"=>show1<="1111001";when"0100"=>show1<="0110011";when"0101"=>show1<="1011011";when"0110"=>show1<="0011111";when"0111"=>show1<="1110000";when"1000"=>show1<="1111111";when"1001"=>show1<="1110011";whenothers=>show1<="0000000";endcase;caseoiswhen"0000"=>show2<="1111110";when"0001"=>show2<="0110000";when"0010"=>show2<="1101101";when"0011"=>show2<="1111001";when"0100"=>show2<="0110011";when"0101"=>show2<="1011011";when"0110"=>show2<="0011111";when"0111"=>show2<="1110000";when"1000"=>show2<="1111111";when"1001"=>show2<="1110011";whenothers=>show2<="0000000";endcase;endif;endprocess;endshumaguanxianshi;動(dòng)態(tài)顯示：libraryIEEE;useIEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_UNSIGNED.ALL;useieee.numeric_std.all;entityshaomiaoxianshiisport<clk,clr:instd_logic;show1:instd_logic_vector<6downto0>;show2:instd_logic_vector<6downto0>;showout:outstd_logic_vector<6downto0>;en:outstd_logic_vector<7downto0>>;endshaomiaoxianshi;architectureshaomiaoxianshiofshaomiaoxianshiissignalcount:std_logic_vector<1downto0>;beginprocess<clk>beginifclr='1'thencount<="00";elseifclk'eventandclk='1'thenifcount="01"thencount<="00";elsecount<=count+'1';endif;endif;ifcount="00"then showout<=show1;en<="00000010";elsifcount="01"then showout<=show2;en<="00000001";endif;endif;endprocess;endshaomiaoxianshi;鍵盤：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitykeyboardisPort<clr:instd_logic;clk:inSTD_LOGIC;keyin:inSTD_LOGIC_VECTOR<3downto0>;keydrv1:outstd_logic_vector<3downto0>;keyvalue:outSTD_LOGIC_VECTOR<4downto0>;start:outstd_logic>;endkeyboard;architectureRTLofkeyboardiscomponentkeyscanPort<clkin,clr:inSTD_LOGIC;keydrv:outSTD_LOGIC_VECTOR<3downto0>>;endcomponent;componentkeydecoderPort<clkin,clk,clr:instd_logic;keyin:inSTD_LOGIC_VECTOR<3downto0>;keycode:outSTD_LOGIC_VECTOR<4downto0>>;endcomponent;componentfangdouport<keycode:instd_logic_vector<4downto0>; keycode1:outstd_logic_vector<4downto0>; start:outstd_logic; clk_f,clr:instd_logic>;endcomponent;componentfredivngeneric<n:integer:=3>;Port<clkin:inSTD_LOGIC;clkout:outSTD_LOGIC>;endcomponent;signalkey2:std_logic_vector<4downto0>;signalclk_temp1:std_logic;signalkey1:std_logic_vector<4downto0>;signalclk_temp2:std_logic;signalstart1:std_logic;beginU1:keyscanportmap<clkin=>clk_temp1,keydrv=>keydrv1,clr=>clr>;U2:keydecoderportmap<clkin=>clk_temp1,keyin=>keyin,keycode=>key1,clk=>clk,clr=>clr>;U3:fredivngenericmap<n=>3>portmap<clkin=>clk,clkout=>clk_temp2>;U4:fredivngenericmap<n=>9>portmap<clkin=>clk,clkout=>clk_temp1>;U5:fangdouportmap<clr=>clr,clk_f=>clk_temp2,keycode=>key1,keycode1=>key2,start=>start1>;process<clk>begin ifrising_edge<clk>then ifclr='0'then keyvalue<=key2;start<=start1; endif; endif;endprocess;endRTL;頂層文件：libraryIEEE;useIEEE.STD_LOGIC_1164.all;entitydingcengisport<clk,clr:instd_logic;keyin:instd_logic_vector<3downto0>;keydrv1:outstd_logic_vector<3downto0>;showout:outstd_logic_vector<6downto0>;en:outstd_logic_vector<7downto0>>;enddingceng;architecturedingcengofdingcengis componentkeyb