Digital Logic Circuits 數(shù)字邏輯電路智慧樹知到期末考試答案章節(jié)答案2024年南京理工大學(xué)

DigitalLogicCircuits數(shù)字邏輯電路智慧樹知到期末考試答案+章節(jié)答案2024年南京理工大學(xué)ANANDgatecanbeconsideredasanANDgatefollowedbyaNOTgate.

答案:對Aliasingisadesiredfactorinsampling.

答案:錯Twocascadeddecadecountersdividetheclockfrequencyby10.

答案:錯MIPSstandsformemoryinstructionspersecond.

答案:錯Deltamodulationisbasedonthedifferenceoftwosuccessivesamples.

答案:對Toachieveamodulusof100,tendecadecountersarerequired.

答案:錯Aserialshiftregisteracceptsonebitatatimeonasingleline.

答案:對TwotypesofSPLDsare

答案:PALandGALIfthepresentstateis1000,thenextstateofa4-bitup/downcounterintheDOWNmodeis0111.

答案:對A5-bitbinarycounterhasamaximummodulusof

答案:32Acounterwithfourstageshasamaximummodulusofsixteen.

答案:對Whichoneofthefollowingisanexampleofacounterwithatruncatedmodulus?

答案:Modulus14Theflip-flopusedinaCPLDmacrocellcanbeprogrammedasa

答案:both(a)and(b)Adigitalsignalprocessingsystemusuallyoperatesin

答案:realtimeThemaximumcumulativedelayofanasynchronouscountermustbe

答案:lessthantheperiodoftheclockwaveformABCDcounterisanexampleof

答案:answers(b)and(c)Inacomputer,theBIOSprogramsarestoredinthe

答案:ROMAregister’sfunctionsinclude

答案:both(a)and(b)Opticalstoragedevicesemploy

答案:lasersAliasingresultsin

答案:undersamplingA3-bitbinarycounterhasamaximummodulusof

答案:8Accordingtothesamplingtheorem,thesamplingfrequencyshouldbe

答案:greaterthantwicethehighestsignalfrequencyAnop-ampisalinearamplifierwhichhas

答案:twoinputsandoneoutputDSPsaretypicallyprogrammedin

答案:both(a)and(b)Theoutputofanexclusive-ORis0iftheinputsareopposite.

答案:錯Aringcounterusesoneflip-flopforeachstateinitssequence.

答案:對Onceprogrammed,PLDlogiccanbechanged.

答案:對InVerilogHDL,~(1010)is(0101),and!(1010)is0.

答案:錯AddressmultiplexingcanreducethenumberofpinsintheICpackage.

答案:對Theprocessofconvertingananalogvaluetoacodeiscalledquantization.

答案:對Fan-outisthenumberofsimilargatesthatagivengatecandrive.

答案:錯OneofthemajorapplicationsofSRAMsisincachememoriesincomputers.

答案:對Toachieveamaximummodulusof32,sixteenstagesarerequired.

答案:錯Fortransmission,datafromaUARTissentinsynchronousparallelform.

答案:錯Acounterwithatruncatedsequencehaslessthanitsmaximumnumberofstates.

答案:對Ashiftregistercannotbeusedtostoredata.

答案:錯LogicsimplificationisstillusefulinnowadaysFPGAdesigns.

答案:錯Successfulapproximationisananalog-to-digitalconversionmethod.

答案:錯Anadditionoverflowsiftheaddends’signsarethesamebutthesum’ssignisdifferentfromtheaddends’.

答案:錯Ashiftregisterwithfourstagescanstoreamaximumcountoffifteen.

答案:對RAMisusedinacomputertostoretheBIOS(BasicInput/OutputSystem

答案:錯Shiftregistersconsistofanarrangementofflip-flops.

答案:對AnADCisananalogdatacomponent.

答案:錯Ananalogsignalcanbeconvertedtoadigitalsignalusingsampling.

答案:對Theinitialstatementexecutesonlyonce,startingfromsimulationtime0,andmaycontinuewithanyoperationsthataredelayedbyagivennumberoftimeunits.

答案:對Ashiftregistercannotbeusedasatimedelaydevice.

答案:錯Toenterabyteofdataseriallyintoan8-bitshiftregister,theremustbe

答案:eightclockpulsesTheoverflowdoesNOToccurwhenaddingthefollowing8-bittwo’scomplementnumber:10111111+11011111

答案:對Memoryexpansionisaccomplishedbyaddinganappropriatenumberofmemorychipstotheaddress,data,andcontrolbuses.

答案:對Witha1MHzclockfrequency,eightbitscanbeparallelenteredintoashiftregister

答案:inthepropagationdelaytimeofoneflip-flopWitha100kHzclockfrequency,eightbitscanbeseriallyenteredintoashiftregisterin

答案:80usTheJohnsoncounterisaspecialtypeofshiftregister.

答案:對Thebitcapacityofamemorythathas512addressesandcanstore8bitsateachaddressis

答案:4096Dataarestoredinarandom-accessmemory(RAM)duringthe

答案:writeoperationTheoutputofaMealymachinedependsonits

答案:inputsTheinitialcountofamodulus-13binarycounteris

答案:0000SRAM,DRAM,flash,andEEPROMareall

答案:semiconductorstoragedevicesInafunctionalsimulation,theusermustspecifythe

答案:inputwaveformsA16-bitwordconsistsof

答案:4nibblesAdigitalvoltmeterusesa

答案:dual-slopeADCA4-bitripplecounterconsistsofflip-flopsthateachhaveapropagationdelayfromclocktoQoutputof12ns.Forthecountertorecyclefrom1111to0000,ittakesatotalof

答案:48nsThequantizationprocess

答案:convertsthesample-and-holdoutputtobinarycodeAbyte-organizedmemoryhas

答案:8dataoutputlineThebasicelementsofanFPGAare

答案:both(a)and(b)NonvolatileFPGAsaregenerallybasedon

答案:antifusetechnologyAmemorywith512addresseshas

答案:9addresslinesThefactorthatdeterminestheadequacyofaGALforalogicdesignis

答案:both(a)and(b)A10MHzclockfrequencyisappliedtoacascadedcounterconsistingofamodulus-5counter,amodulus-8counter,andtwomodulus-10counters.Thelowestoutputfrequencypossibleis

答案:2.5kHzAmodulus-12countermusthave

答案:4flip-flopsThemodulusofacounteris

答案:theactualnumberofstatesinitssequenceGenerally,ananalogsignalcanbereconstructedmoreaccuratelywith

答案:eitheranswer(a)or(c)AROMisa

答案:nonvolatilememoryThreecascadedmodulus-10countershaveanoverallmodulusof

答案:1000Thegroupofbits10110101isseriallyshifted(right-mostbitfirst)intoan8-bitparalleloutputshiftregisterwithaninitialstateof11100100.Aftertwoclockpulses,theregistercontains

答案:01111001The(

)oftheA/Dconverterdetermineshowclosetheactualdigitaloutputistothetheoreticallyexpecteddigitaloutputforagivenanaloginput.

答案:accuracyAreconstructionfilter(

).

答案:alloftheaboveAhighersamplingrateismoreaccuratethanalowersamplingrateforagivenanalogsignal.

答案:對Ifananti-aliasingfilterisnotusedindigitizingasignaltherecoveryprocess(

)

答案:mayincludealiassignalsTwotypesofDACarethebinary-weightedinputandtheR/2Rladder.

答案:對AnADCisananalogdatacomponent

答案:錯The()ofADCisdeterminedbythenumberofbitsitusestodigitizeaninputsignal.

答案:resolutionTheIntegralNonlinearityofanADCdefinesthemaximumdeviationoftheADCtransferfunctionfromthebest-fitline.

答案:對Ananti-aliasingfiltershouldhave(

)

答案:Thenumberofcomparatorsrequiredina10-bitflashADCis(

).

答案:1023Memoryexpansion

isaccomplishedbyaddinganappropriatenumberofmemorychipstotheaddress,data,

andcontrolbuses.

答案:對A4-bitparallel-in/parallel-outshiftregisterwillstoredatafor(

).

答案:1clockperiodStaticRAMis(

).

答案:volatileread/writememoryWhendataisreadfromRAM,thememorylocationis(

).

答案:unchangedRAMisusedinacomputerto

storetheBIOS(BasicInput/Output

System.

答案:錯TheadvantageofdynamicRAMoverstaticRAMisthat(

).

答案:itissimplerandcheaperThefirststepinareadorwriteoperationforarandomaccessmemoryisto(

).

答案:placeavalidaddressontheaddressbusAnonvolatilememoryisonethat(

)

答案:retainsdatawithoutpowerappliedAnadvantageofaringcounteroveraJohnsoncounteristhattheringcounter(

).

答案:isself-decodingAssumetheclockfora4-bitbinarycounteris80kHz.Theoutputfrequencyofthefourthstage(Q3)is(

).

答案:5kHzApossiblesequencefora4-bitringcounteris(

).

答案:…1000,0100,0010…A4-bitbinarycounterhasaterminalcountof(

).

答案:15Themaximummodulusofacounteris,

wherenisthenumberofstages(flip-flops)inthecounter.

答案:錯Fortransmission,datafromaUARTissentin

synchronousparallelform.

答案:錯Forcounterswithunusedstates,itisnecessarytoensurethatthecircuiteventuallygoesintooneofthevalidstatessothatitcanresumenormaloperation.

答案:對TocauseaDflip-floptotoggle,connectthe(

).

答案:Adivide‐by‐N-counterisacounterthatgoesthrougharepeated

sequenceofNstates,anditisalsoknownasamodulo‐Ncounter.

答案:對TheoutputofaDlatchwillnotchangeif(

).

答案:EnableisnotactiveFortheJ-Kflip-flopshown,thenumberofinputsthatareasynchronousis(

).

答案:2InaMoore

model,theoutputsofthesequentialcircuitarenotsynchronizedwiththe

clock.

答案:錯TheDflip-flopshownwill(

).

答案:toggleonthenextclockpulseThetimeintervalillustratediscalled(

).

答案:tPLHAssumetheoutputisinitiallyHIGHonaleadingedgetriggeredJ-Kflipflop.Fortheinputsshown,theoutputwillgofromHIGHtoLOWonwhichclockpulse?

答案:3TheadvantageofdynamicRAMoverstaticRAMisthat(

).

答案:itissimplerandcheaperTheoutputoftheMealy

machineisthevaluethatispresentimmediatelybeforethe

activeedgeoftheclock.

答案:對InVerilogHDL,aninitialbehavioralstatementexecutesonlyonce.

答案:對Anasynchronous

resetsignalwilloverridetheclockonaFF.

答案:對ThecontinuousassignmentassignOUT=

select?A:B;specifiestheconditionthatOUT=

()

ifselect=

1,elseOUT=

()

ifselect=

0.

答案:A,BToexpanda2-bitparalleladdertoa4-bitparalleladder,youmust(

).

答案:usetwo2-bitadderswiththecarryoutputofoneconnectedtothecarryinputoftheotherTheinitialstatementexecutesonlyonce,startingfrom

simulationtime0,andmaycontinuewithanyoperationsthataredelayedbyagiven

numberoftimeunits.

答案:對Ifanhex-to-binarypriorityencoderhasits0,3,6,and14inputsattheactivelevel,theactive-HIGHbinaryoutputis(

).

答案:1110The74138decodercanalsobeusedas(

).

答案:aDEMUXAssumeyouwanttodecodethebinarynumber0011withanactive-LOWdecoder.Themissinggateshouldbe(

).

答案:aNANDgateConsidertheinitial

blockinthefollowing:initialbeginA=0;B=0;#10A=1;#20A=0;B=1;EndThenatt=30,Ais

changedto(

)andBto(

).

答案:0,1InVerilogHDL,thedefinitionsofmodulesareallowedtobenested.

答案:錯ThevaluezrepresentsanunknownlogicvalueinVerilogHDL.

答案:錯SOPstandardformisusefulforconstructingtruthtablesorforimplementinglogicinPLDs.

答案:對AdjacentcellsonaKarnaughmapdifferfromeachotherby

答案:onevariableInsynthesis,anetlistwillbegeneratedtodescribethecircuitcompletely.

答案:對TheBooleanequationAB+AC=A(B+C)illustrates(

)

答案:thedistributionlawTheBooleanexpressionA

+1isequalto(

).

答案:1TheBooleanexpressionA

.

1isequalto(

).

答案:ATheassociativelawforadditionisnormallywrittenas(

)

答案:(A+B)+C

=A

+(B+C)InFPGAdesign,thestepthat“maps”thedesignfromthenetlisttofitittoatargetdeviceisknownas"programming".

答案:錯ABooleanexpressionthatisinstandardSOPformis(

)

答案:haseveryvariableinthedomainineverytermThefractionalbinarynumber0.11hasadecimalvalueof(

)

答案:?TheoverflowdoesNOToccurwhenaddingthefollowing8-bittwo’scomplementnum