chap5-1-Combin.ppt

1、Examples of Basic Combinational,Logic Circuit Design,Teacher：Shan Liang Email: Office: 506 Telephone:86835768,5.1 Basic Combinational Logic Circuits Design 5.1.1 Verilog for Basic Gate Circuit 5.1.2 Verilog for Multiplexer( Data Selector) 5.1.3 Verilog for Adder 5.1.4 Verilog for Priority Encoder 5.

2、1.5 Verilog for Decoder 5.1.6 Verilog for Parity Check 5.1.7 Verilog for ROM,Contents,Combinational Circuit Design,Outputs are functions of inputs in combinational logic circuits.,Examples: - gate circuit - multiplexer - decoder - priority encoder - parity check - adder - ROM,5.1.1 Basic Gate Circui

3、t -(I),Example: Describe the gate circuit with structural method, data flow method and behavioral method.,structural method,module gate1(F,A,B,C); input A,B,C; output F; and(F1,A,B); nor(F2,A,C); xor(F,F1,F2); endmodule,data flow method,module gate2(F,A,B,C); input A,B,C; output F; assign F=(A endmo

4、dule,behavioral method,module gate3(F,A,B,C); input A,B,C; output F; reg F; always (A or B or C) begin F=(A end endmodule,Basic Gate Circuit -(II),module tri_1(in,en,out); input in,en; output out; tri out; bufif1 b1(out,in,en); endmodule,Example: Describe a three-state gate with keyword bufif1.,Exam

5、ple: Describe a three-state gate with data flow method.,module tri_2(in,en,out); input in,en; output out; assign out=en?in:bz; endmodule,5.1.2 Multiplexer,Multiplexor is a combinational circuit where an input is chosen by a select signal. Two input mux output =A if select =1 output= B if select =0,A

6、,B,x,s,Select input,2-1 Multiplexer,A two-input mux is actually a three input device.,F = A.s + B.s,Truth Table,2-1 Multiplexer,module mux2_1 (out,a,b,sel) ; output out ; input a,b,sel ; nor (sel_, sel) ; and (a1, a, sel_) ; and (b1, b, sel) ; or (out, a1, b1) ; endmodule,Net-list (gate-level),2-1 M

7、ultiplexer,Continuous assignment module mux2_1 (out,a,b,sel) ; output out ; input a,b,sel ; assign out = (a,module mux4_1(out,in0,in1,in2,in3,sel); output out; input in0,in1,in2,in3; input1:0 sel; reg out; always (in0 or in1 or in2 or in3 or sel) begin if(sel=2b00) out=in0; else if(sel=2b01) out=in1

8、; else if(sel=2b10) out=in2; else out=in3; end endmodule,4-1 Multiplexer,Example: A 4-1 mux with if-else sentence.,Module mux8_1(dout,sel,d0,d1,d2,d3,d4,d5,d6,d7); Input d0,d1,d2,d3,d4,d5,d6,d7; Inpur2:0 sel; Output dout; Always ( d0 or d1 or d2 or d3 or d4 or d5 or d6 or d7 or sel) Begin Case (sel)

9、 3d0: dout=d0; 3d1: dout=d1; 3d2: dout=d2;,8-1 Multiplexer,3d3: dout=d3; 3d4: dout=d4; 3d5: dout=d5; 3d6: dout=d6; 3d7: dout=d7; Default: dout=1bx; Endcase End Endmodule,8-1 Multiplexer,5.1.3 Adder,RTL modeling module adder(c,s,a,b) ; output c ; output 7:0 s ; input 7:0 a,b ; assign c,s = a + b ; en

10、dmodule,module add4 (s,c3,ci,a,b); input 3:0 a,b ; input ci ; output 3:0 s : output c3 ; wire 2:0 co ; add a0 (co0, s0, a0, b0, ci) ; add a1 (co1, s1, a1, b1, co0) ; add a2 (co2, s2, a2, b2, co1) ; add a3 (c3, s3, a3, b3, co2) ; endmodule,Example: 4-bit full adder,module add(cout,sum,a,b,cin); input

11、 a,b,cin; output sum,cout; assign cout,sum=a+b+cin; endmodule,module add (co, s, a, b, c)； input a, b ,c ; output co, s ; xor (n1, a, b) ; xor (s, n1, c) ; nand (n2, a, b) ; nand (n3,n1, c) ; nand (co, n3,n2) ; endmodule,A full-adder,Gate level structure description,5.1.4 Priority Encoders,module en

12、coder83(out,a,b,c,d,e,f,g,h); output2:0 out; input a,b,c,d,e,f,g,h; reg2:0 out; always(a or b or c or d or e or f or g or h) begin if(h) out=3b111; else if(g) out=3b110; else if(f) out=3b101; else if(e) out=3b100; else if(d) out=3b011; else if(c) out=3b010; else if(b) out=3b001; else out=3b000; end

13、endmodule,module encoder_83(din,dout); input7:0 din; output2:0 dout; function2:0 code; input7:0 din; casex (din) 8b1xxx_xxxx : code = 3h7; 8b01xx_xxxx : code = 3h6; 8b001x_xxxx : code = 3h5; 8b0001_xxxx : code = 3h4; 8b0000_1xxx : code = 3h3; 8b0000_01xx : code = 3h2; 8b0000_001x : code = 3h1; 8b000

14、0_0001 : code = 3h0; default: code = 3hx; endcase endfunction assign dout = code(din) ; endmodule,5.1.5 decoder,設二進制譯碼器的輸入端為n個，則輸出端為2n個，且對應于輸入代碼的每一種狀態(tài)，2n個輸出中只有一個為1（或為0），其余全為0（或為1）,module decoder_38(out,in); output7:0 out; input2:0 in; reg7:0 out; always (in) begin case(in) 3d0: out=8b00000001; 3d1:

15、out=8b00000010; 3d2: out=8b00000100; 3d3: out=8b00001000; 3d4: out=8b00010000; 3d5: out=8b00100000; 3d6: out=8b01000000; 3d7: out=8b10000000; endcase end endmodule,module parity(even_bit,odd_bit,input_bus); output even_bit,odd_bit; input7:0 input_bus; assign even_bit=input_bus; /偶校驗位 assign odd_bit=

16、even_bit;/奇校驗位 endmodule,Example: A parity check bit generator.,5.1.6 parity check,5.1.7 ROM,Example: A ROM realized by combinational circuit.,9: romout=81; 10: romout=100; 11: romout=121; 12: romout=144; 13: romout=169; 14: romout=196; 15: romout=225; default: romout=8hxx; endcase endfunction assig

17、n data=romout(addr); endmodule,module rom(addr,data); input3:0 addr; output7:0 data; function7:0 romout; input3:0 addr; case(addr) 0: romout=0; 1: romout=1; 2: romout=4; 3: romout=9; 4: romout=16; 5: romout=25; 6: romout=36; 7: romout=49; 8: romout=64;,Exercises,5-1Write Verilog code to describe 4-to-1 Multiplexer, Using Logic Equations. 5-2Verilog code for a four-bit adder