verilog編寫的基本電路邏輯及仿真

1、集成電路與verilog語言實驗報告集成電路與Verilog語言 實驗1：分別用門級建模、數(shù)據(jù)流級建模、和行為級建模實現(xiàn)一個2選1的MUX，兩個輸入端分別為A和B，當(dāng)選擇端SEL=0時，輸出F選擇A；當(dāng)選擇端SEL=1時，輸出F選擇B。ABSEL門級建模：源代碼：/MUX2to1 gatelevelmodule MUX_gate(a,b,sel,f); input a; input b; input sel; output f; reg f;wire nsel,y1,y2;not unot(nsel,sel);and u1and(y1,a,nsel);and u2and(y2,b,sel);o

2、r uor(f,y1,y2);endmodule綜合結(jié)果：TB代碼：module tb_MUX_gate;/ Inputsreg a;reg b;reg sel;/ Outputswire f;/ Instantiate the Unit Under Test (UUT)MUX_gate uut (.a(a), .b(b), .sel(sel), .f(f);initial begin/ Initialize Inputsa = 0;b = 0;sel = 0;/ Wait 100 ns for global reset to finish#10/ Add stimulus herea=1;b

3、=0;sel=0;#10; a=1;b=0;sel=1;#10;#10$finish;endendmodule仿真結(jié)果：數(shù)據(jù)流級建模：源代碼：/MUX2to1 datapromodule MUX_datapro(a,b,sel,f); input a; input b; input sel; output f;reg f;wire nsel,y1,y2;assign nsel=sel;assign y1=a&nsel;assign y2=b&sel;assign f=y1|y2; endmodule綜合結(jié)果：TB代碼：module tb_MUX_datarpro;/ Input

4、sreg a;reg b;reg sel;/ Outputswire f;/ Instantiate the Unit Under Test (UUT)MUX_datapro uut (.a(a), .b(b), .sel(sel), .f(f);initial begin/ Initialize Inputsa = 0;b = 0;sel = 0;/ Wait 100 ns for global reset to finish#10; / Add stimulus herea=1;b=0;sel=0;#10; a=1;b=0;sel=1;#10;#10$finish;enendmodule仿

5、真結(jié)果：行為級建模：源代碼：/MUX2to1 behavmodule MUX_behav(f,a,b,sel);input a,b,sel;output f;reg f;reg y1,y2,nsel;always (a or b or sel)begin nsel <=sel; y1 <= a&nsel; y2 <= b&sel; f <= y1|y2; endendmodule綜合結(jié)果：TB代碼：module tb_MUX_behav;/ Inputsreg a;reg b;reg sel;/ Outputswire f;/ Instantiate t

6、he Unit Under Test (UUT)MUX_behav uut (.a(a), .b(b), .sel(sel), .f(f);initial begin/ Initialize Inputsa = 0;b = 0;sel = 0;/ Wait 100 ns for global reset to finish#10; / Add stimulus herea=1;b=0;sel=0;#10; a=1;b=0;sel=1;#10;#10$finish;end endmodule仿真結(jié)果：實驗2題目：實現(xiàn)一個計數(shù)器，計數(shù)時計數(shù)器可從0計到10。源代碼：module counter(d

7、in,up1_down0,clk,nrst,sta1_pau0,load,counter); input3:0 din; input up1_down0; input clk; input nrst; input sta1_pau0; input load; output 3:0 counter; reg 3:0 counter;always (posedge clk or negedge nrst)begin if(nrst) counter <= 4'b0000; else if(load) counter <= din; else begin if(sta1_pau0

8、) counter <= counter; else if(up1_down0) if (counter = 10) counter <= 4'b0000; else counter <= counter + 1;else if (counter = 0) counter <= 4'b1010; else counter <= counter - 1; end endendmodule綜合結(jié)果：TB代碼：module tb2;/ Inputsreg 3:0 din;reg up1_down0;reg clk;reg nrst;reg sta1_pa

9、u0;reg load;/ Outputswire 3:0 counter;/ Instantiate the Unit Under Test (UUT)counter uut (.din(din), .up1_down0(up1_down0), .clk(clk), .nrst(nrst), .sta1_pau0(sta1_pau0), .load(load), .counter(counter); initial clk = 1'b0; always #5 clk = clk;initial begin/ Initialize Inputsdin = 0;up1_down0 = 0

10、;nrst = 0; sta1_pau0 = 0;load = 0;/ Wait 100 ns for global reset to finish#50;/ Add stimulus here/從0開始加計數(shù) din = 4'b0111;nrst = 1; up1_down0 = 1;sta1_pau0 = 1;#210;/暫停sta1_pau0 = 0; #20;/從7開始減計數(shù)load = 1; #10; load = 0;sta1_pau0 = 1; up1_down0 = 0;#200;#20 $finish;end endmodule仿真結(jié)果：實驗3題目：由Morre狀態(tài)機

11、設(shè)計一個簡單的交通燈，假定紅燈時間為9個時間單位，綠燈時間為6個時間單位，黃燈時間為3個時間單位。源代碼：module light_machine(clk,nrst,y,t); input clk; input nrst; output 1:0 y; output 3:0 t; reg 3:0 q; reg 1:0 y; reg 1:0 state; reg 3:0 t; parameter green = 2'b00,yellow = 2'b01,red = 2'b11;initial begin q <= 4'b0; t <= 4'b0;

12、endalways (posedge clk or negedge nrst)begin if(!nrst) begin state <= green; y <= 2'bz; end else case(state) green: begin q <= q +1; t <= q; if(q = 5) begin q <= 4'b0; state <= yellow; end else begin y <= 2'b00; state <= green; end end yellow: begin q <= q +1;

13、t <= q; if (q = 2) begin q <= 4'b0; state <= red;end else begin y <= 2'b01; state <= yellow; end end red: begin q <= q + 1; t <= q; if (q = 8) begin q <= 4'b0; state <= green;end else beginy <= 2'b11;state <= red;end end endcaseendendmodule綜合結(jié)果：TB代碼：m

14、odule tb_2;/ Inputsreg clk;reg nrst;/ Outputswire 1:0 y;wire 3:0 t;/ Instantiate the Unit Under Test (UUT)light_machine uut (.clk(clk), .nrst(nrst), .y(y), .t(t); initial clk = 1'b0; always #5 clk = clk; initial begin/ Initialize Inputsnrst = 0;/ Wait 100 ns for global reset to finish#30; / Add

15、stimulus herenrst = 1;#500;#20$finish;end endmodule仿真結(jié)果：實驗4題目：對一個400MHz的時鐘分別完成2、4、8分頻。源代碼：module divclk(clkin,nrst,din, clkout); input clkin; input nrst; input 1:0 din; output clkout; reg 28:0 q; reg clkout; initialbegin q <=29'b0;end always (posedge clkin or negedge nrst)begin if(nrst) q <

16、;= 29'b0; else q <= q + 29'b1; endalways (posedge clkin)begin case(din) 2'b00: clkout <= q0; 2'b01: clkout <= q1; 2'b10: clkout <= q2; default: clkout <= 1'bz; endcaseendendmodule綜合結(jié)果：TB文件：module tb_div;/ Inputsreg clkin;reg nrst;reg 1:0 din;/ Outputswire clkou

17、t;/ Instantiate the Unit Under Test (UUT)divclk uut (.clkin(clkin), .nrst(nrst), .din(din), .clkout(clkout); initial clkin = 1'b0; always #1.25 clkin = clkin; initial begin/ Initialize Inputsnrst = 0;din = 2'b11;/ Wait 100 ns for global reset to finish#50; / Add stimulus herenrst = 1;din = 2

18、'b00;#50;din = 2'b01;#50;din = 2'b10;#50;din = 2'b11;#50;#20$finish;end endmodule仿真結(jié)果：實驗5題目：按照病情嚴重程度將8名病人分配到8個病房，1號病房病情最輕，8號病房病人病情最嚴重。每個病房有一個按鈕用于呼叫醫(yī)生，在醫(yī)生辦公室有個顯示屏，用于顯示哪個病房按了按鈕。由于病情不同，要求當(dāng)病情較嚴重的病房按了按鈕后，醫(yī)生辦公室的顯示屏要優(yōu)先顯示其病房號。源代碼：module priority_encoder(clk,I0,I1,I2,I3,I4,I5,I6,I7,Y); input

19、clk; input I0; input I1; input I2; input I3; input I4; input I5; input I6; input I7; output 2:0 Y; reg 2:0 Y;always (posedge clk )begin if(I7) Y <= 3'b111; else if(I6) Y <= 3'b110; else if(I5) Y <= 3'b101; else if(I4) Y <= 3'b100; else if(I3) Y <= 3'b011; else if(I2) Y <= 3'b010; else if(I1) Y <= 3'b001; else if(I0) Y <= 3'b000; else Y <= 3