本章只要求存儲(chǔ)器中的ROM及其用于組合邏輯電路的設(shè)計(jì)

1、2022-2-16Chapter 9 Memory、CPLD and FPGA本章只要求存儲(chǔ)器中的本章只要求存儲(chǔ)器中的ROM及其用及其用于組合邏輯電路的設(shè)計(jì)于組合邏輯電路的設(shè)計(jì)2022-2-16chapter 92022-2-16chapter 9memorymemoryROM (read-only memory)RAM(random-access memory)Non-volatile while powered downVolatile while powered downOften be used store firmware or initial program of the comp

2、uterData exchange and storing temporarily in CPU or other microprocessormemory：store bits in a structured way2022-2-16chapter 99.1 Read-Only Memory (ROM)9.1 Read-Only Memory (ROM) 1. basic strcture2nb ROMn-bit address inputb-bit data outputA0A1A2An-2An-1D0D1Db-1D0Db-1000n-bit address001111b-bit data

3、sketch map of RAM2022-2-16chapter 92. Internal ROM structurestorage array（Mb）01M-1address input Row (address) decoderA0A1An-1D0Db-1output circuitData output2022-2-16chapter 9word line bit lineaddress decoder輸出電路輸出電路address inputa data stored unitdata stored arrayData outputhas diode: store 1no diode

4、: store 084 ROM structure2022-2-16chapter 93. Two-dimensional decoding1281ROM000000000011110010000001111111100001111111地址地址2022-2-16chapter 9MOS transistors as storage elementsMOS transistors as storage elements2022-2-16chapter 94. commercial ROM types4. commercial ROM types mask-programmable ROM ar

5、ray connections are programmed during semiconductor manufacture using a mask. very fast. very dense. expensive, 2-4 week turn-around, low power Programmable ROM(PROM) fuses to program once in the field, use PROM programmer, inexpensiveword linebit linefuse2022-2-16chapter 9 EPROM（Erasable PROM） fuse

6、s implemented using floating-gate MOS transistors to program 10k100k times in the field, erased by flooding with UV light. E2PROM（Electrically EPROM） byte-program, individual stored bits may be erased electrically. 2764(8k8), 27128(16k8), 27256(32k8), 27512(64k8) flash E2PROM a specific type of E2PR

7、OM that is erased and programmed in large blocks (NOR type and NAND type)2022-2-16chapter 9floating-gate MOS storage elementsfloating-gate MOS storage elementserased by UV light2022-2-16chapter 9 按照數(shù)據(jù)的輸入按照數(shù)據(jù)的輸入/輸出分為串行輸出分為串行EEPROM和并和并行行EEPROM。 串行串行EEPROM：在讀寫(xiě)數(shù)據(jù)時(shí)，輸入：在讀寫(xiě)數(shù)據(jù)時(shí)，輸入/輸出時(shí)通過(guò)輸出時(shí)通過(guò)2線、線、3線、線、4線或線或S

8、PI總線等接口方式進(jìn)行的?？偩€等接口方式進(jìn)行的。 并行并行EEPROM：數(shù)據(jù)的輸入：數(shù)據(jù)的輸入/輸出是通過(guò)并行總線輸出是通過(guò)并行總線進(jìn)行的。進(jìn)行的。 近期，低功耗，寫(xiě)入近期，低功耗，寫(xiě)入/擦除速度快的產(chǎn)品很多，擦除速度快的產(chǎn)品很多，如如Microchip公司的新型公司的新型8千位、千位、16千位串行千位串行EEPROM，最快時(shí)鐘，最快時(shí)鐘10MHZ，寫(xiě)入時(shí)間，寫(xiě)入時(shí)間5ms，電流電流3mA,內(nèi)置寫(xiě)保護(hù)功能，可保存數(shù)據(jù)達(dá)內(nèi)置寫(xiě)保護(hù)功能，可保存數(shù)據(jù)達(dá)200年，承受年，承受100萬(wàn)次擦寫(xiě)。萬(wàn)次擦寫(xiě)。Atmel公司的公司的AT24C系列系列2022-2-16chapter 95. Using ROM

9、for “random” combinational logic functions Store the output value of a given truth table in the ROM, the function inputs are connected to the address input .Exp1: the dual polarity decoder.(P.801)POLI1I0Y3 Y2 Y1 Y00000111001101101011010111110100100010101001100010111000184 ROMA0A1A2D0D1D3D2POLI1I0Y0Y

10、1Y2Y32022-2-16chapter 9Exp2: 4Exp2: 44 multiplier4 multiplier每行第一個(gè)每行第一個(gè)數(shù)據(jù)單元的數(shù)據(jù)單元的地址地址每行包含每行包含16個(gè)數(shù)據(jù)單元的數(shù)據(jù)個(gè)數(shù)據(jù)單元的數(shù)據(jù)2022-2-16chapter 9More Exp.: ROM在同步時(shí)序電路設(shè)計(jì)中的應(yīng)用在同步時(shí)序電路設(shè)計(jì)中的應(yīng)用位序列信號(hào)的產(chǎn)生：計(jì)數(shù)器位序列信號(hào)的產(chǎn)生：計(jì)數(shù)器 ROM法法設(shè)計(jì)一個(gè)碼長(zhǎng)為設(shè)計(jì)一個(gè)碼長(zhǎng)為8位的序列信號(hào)發(fā)生器，信號(hào)序列位的序列信號(hào)發(fā)生器，信號(hào)序列為為01111110。CLKCLRLDENPENTDCBAQCQDQBQARCOADD2ADD1ADD0 SEQ V

11、CCCLKD0D1D2D384ROM2022-2-16chapter 9addressQC QB QAROM中存儲(chǔ)的數(shù)中存儲(chǔ)的數(shù)據(jù)據(jù) D3D0000000000100010100001011000110000011010001110000111100002022-2-16chapter 9ROM在組合電路設(shè)計(jì)中的應(yīng)用在組合電路設(shè)計(jì)中的應(yīng)用 試用試用84ROM實(shí)現(xiàn)如下組合邏輯函數(shù)實(shí)現(xiàn)如下組合邏輯函數(shù) F1=AB+AC, F2=AB+BC解：先化作標(biāo)準(zhǔn)和式解：先化作標(biāo)準(zhǔn)和式 以輸入變量作為以輸入變量作為ROM的地址，將輸出值的地址，將輸出值放入放入ROM單元。單元。 用用16字字4位位ROM實(shí)現(xiàn)實(shí)

12、現(xiàn)2輸入變量的與非、輸入變量的與非、或非、異或和同或或非、異或和同或 實(shí)現(xiàn)實(shí)現(xiàn)4位二進(jìn)制碼位二進(jìn)制碼格雷碼的轉(zhuǎn)換格雷碼的轉(zhuǎn)換2022-2-16chapter 9Random-access memory (RAM)Random-access memory (RAM)Static RAMDynamic RAMboth are volatileRandom access means:locations in the memory can be written to or read from in any order, regardless of the memory location that wa

13、s last accessed.store a bit of data in the state of a flip-flopstore a bit of data as a charge in a capacitor2022-2-16chapter 99.3 Static Random-Access Memory 2nb RAM structureA0A1Din0An-2An-1D0D1Db-1Dinb-1CSOEWEAddress inputsData inputsControl inputsData outputsD0Db-1000An-1A0001111CS、OE有效，有效，b位數(shù)據(jù)輸

14、出位數(shù)據(jù)輸出CS、WE有效，有效，b位數(shù)據(jù)輸入位數(shù)據(jù)輸入2022-2-16chapter 9SRAM internal structureSRAM internal structureAddress decoderA0A1An-1Storage array(Mb)D0Db-1Output circuit01M-1D0Db-1WR/RDcontrolWE_LCS_LOE_L2022-2-16chapter 9A static-RAM cell SEL_L、WR_L both negated, D latch hold the data； SEL_L is asserted, tri-state

15、buffer enable, data output (read); SEL_L、WR_L both be asserted, D latch open, a new bit is stored.store a bit of data in the state of a flip-flop2022-2-16chapter 9synchronous SRAMsynchronous SRAM A bit of storage is also a latch. Put registers in front of address and control (and maybe data) for eas

16、ier interfacing with synchronous systems at high speeds2022-2-16chapter 99.4 dynamic RAMWrite: Charge the capacitor- store 1;Discharge the capacitor-store 0.Read:- Precharge bit line to VDD/2.- Take the word line HIGH.- Detect whether current flows into or out of the cell.- Note: cell contents are d

17、estroyed by the read!- Must write the bit value back after reading.store a bit of data in a separate capacitor through a MOS transistor, and need to be refreshed periodically.2022-2-16chapter 92022-2-16chapter 9SDRAMSDRAM Control and data operations are referenced to a common clock signal. 是是single

18、data rate, 與系統(tǒng)總線速度同步，在一與系統(tǒng)總線速度同步，在一個(gè)時(shí)鐘周期的上升沿傳輸一次數(shù)據(jù)。個(gè)時(shí)鐘周期的上升沿傳輸一次數(shù)據(jù)。 曾經(jīng)是曾經(jīng)是PC電腦上最為廣泛應(yīng)用的一種電腦上最為廣泛應(yīng)用的一種內(nèi)存類型內(nèi)存類型 ，分為分為PC66、PC100、PC133等不同規(guī)格，而規(guī)等不同規(guī)格，而規(guī)格后面的數(shù)字就代表著該內(nèi)存最大所能正常工作格后面的數(shù)字就代表著該內(nèi)存最大所能正常工作系統(tǒng)總線速度系統(tǒng)總線速度 2022-2-16chapter 9 雙數(shù)據(jù)傳輸模式雙數(shù)據(jù)傳輸模式同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器，即同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器，即DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) 是一種繼是一種繼SDRAM后產(chǎn)生的后產(chǎn)生的內(nèi)存內(nèi)存技術(shù)，為具有雙技術(shù)，為具有雙倍數(shù)據(jù)傳輸率之倍數(shù)據(jù)傳輸率之SDRAM，其數(shù)