信號完整性分析_過孔、連接器、封裝

1、信號完整性分析信號完整性分析Signal Integrity 第五講：過孔、連接器、封裝Vias, Connectors, and Packages第五講: 過孔、連接器、封裝Suggested Reading:1 S Hall, G Hall, and J McCall, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practice, Chapters 5 & 11 John Wiley & Sons, 2000.2 H Johnson and M Graham,

2、 High-Speed Digital Design: A handbook of Black Magic, Chapters 7 & 9, Prentice Hall, 1993.3 B Young, Digital Signal Integrity, Chapter 2, Prentice Hall, 2001.How are signal getting from one chip to another?Pentium 4 CPU goes here(socket)Memory ConnectorBridgechipVias, connectors, and packages a

3、re all important and necessary parts of the path. Bridge chip packageTopics Vias Definition: what are they and why do we need them? Electrical models of via parasiticsConnectors Definition: what are they and why do we need them? Electrical effects Inductance SLEM-style approximation Power and ground

4、 pins Design considerations (tradeoffs, rules of thumb)Topics (continued)Packages Definition: what they are and why we need them? Common types (e.g. flip-chip, bondwire) and history Creating package models Effect of a package on signal integrity Design considerationsl Vertical connections between la

5、yers made by drilling a small hole and filling it with conductive material. Connecting metal layers on silicon chips, within packages, and on printed circuit boards.capacitorchipchipPrinted Circuit BoardViasVias Barrel: conductive cylinder filling the drilled hole Pad: connects the barrel to the com

6、ponent/plane/trace Antipad: clearance hole between via and no-connect metal layerBarrelPadVia pad does not contact plane; void is the anti-padTrace connected to pad on layer 1.Via: Vertical Connection between LayersPadq Connect metal planes of the same potential (e.g., all ground planes conductively

7、 attached)q Carry a signal from a trace on one layer to another (e.g., every data signal must get from the silicon bump down to the motherboard)q Connect components (such as a capacitor) to a signal trace or a voltage plane.What Can a Via Do?PCB Via TypesPCB Via Types過孔(Via)l 過孔在多層PCB設計中非常重要，一個過孔主要由

8、三部分組成：1. 孔；2. 孔周圍的焊盤區(qū)；3. POWER和GROUND層的隔離區(qū)。l 過孔的工藝過程過孔壁圓柱面上用化學沉積的方法鍍上一層金屬，用以連通中間各層需要連通的銅箔；過孔的上下兩面做成普通的焊盤形狀，可直接與上下兩面的線路相通，也可不連；過孔可以起到電氣連接、固定或定位器件的作用。PCB Via Types過孔一般又分為三類：盲孔、埋孔和通孔。l 盲孔指位于印刷線路板的頂層和底層表面，具有一定深度，用于表層線路和下面的內(nèi)層線路的連接，孔的深度與孔徑通常不超過一定的比率。l 埋孔，,指位于印刷線路板內(nèi)層的連接孔，它不會延伸到線路板的表面。 (盲孔與埋孔兩類孔都位于線路板的內(nèi)層，層壓

9、前完成。)l 通孔，這種孔穿過整個線路板，可用于實現(xiàn)內(nèi)部互連或作為元件的安裝定位孔,大都是層壓后完成。由于通孔在工藝上更易于實現(xiàn)，成本較低，所以一般印制電路板都使用通孔。SEM (Scanning Electronic Micrograph) Cross-Section Images Laser generated viaPhoto-defined viaPlasma generated viaCond. ink filled via激光打孔技術等離子干腐蝕技術More SEM Cross-section ImagesMicroviaPlated-through holeL_barrelC_p

10、adC_padl Vias are tiny structures unless Tvia delay 1/10 signal edgel The via can be modeled as a lumped pi-model.To dark pink t-lineTo pink t-lineEquivalent Circuit Model of a ViaSame as low pass filter Cascading ElementsL_barrelC_padC_padL_barrelC_padTraceconnectionTraceconnectionVia Capacitance E

11、ffect is to slow the edge Empirical formula for pad capacitance:Via Inductance Series L degrades signal integrity Empirical formula for barrel inductance:121411DDTDCrvia. 14ln08. 5dhhLviaD1: Via pad diameterD2: Via anti-pad diameterT: PCB thicknessh: via lengthd: barrel diameterVia Induced Delay cap

12、acitive loading + inductive loading + added distanceExample 1Model parasitics of vias Ladder Model LCs are good to 1-2 GHzGNDPWRZ01Z01Z02Example 2200 MHz model parasitics of via stubGNDPWRLZ02Z01Z03via up to another signal layerSNG1SNG2Example 3Overall S-parameters can be obtained by the sub-network

13、s using the ABCD or chain scattering matrixes.GNDPWRS02(f)Svia(f)S01(f)ConnectorsPentium III and Pentium II processor-based NLX motherboard supporting 66-MHz and 100-MHz System BusesVertically (new PCB perpendicular to mb)Horizontal (new PCB parallel to mb)Electrically/Mechanically connect one PCB b

14、oard or PKG to another.Edge ConnectorsISAISA =Industry Standard Architecture Edge ConnectorsDIMMDIMM=Dual-Inline-Memory-ModulesEdge ConnectorsPCIPCI= Peripheral Component InterconnectEdge ConnectorsSLOT1APGPGA370PGA (Pin Grid Array) Sockets 2D or 3D field solvers (HFSS) for better modeling Series or

15、 mutual inductance have major effects 1st order value can be estimated using empirical formulas Series L slows edge Complicated coupling introducing noise Shunt or mutual capacitance Slows the system edge rate Capacitors sometimes added to reduce impedance discontinuity at connector Connector crosst

16、alk Because of geometry, mutual L has larger effect than mutual C. For first-order estimation, just consider L.Connector “Parasitic” ParametersConnector Effects214ln2432ln2nHpllLnHrllLoo r l r radius of round wire l length p perimeter of rectangular wireApproximation of mutual L between 2 connector

17、pins12ln211ln222nHsllLnHlslsslsllLomom sDIPPLCCQFPBGA CSP； 材料方面：金屬、陶瓷陶瓷、塑料塑料； 引腳形狀：長引線直插短引線或無引線貼裝球狀凸點； 裝配方式：通孔插裝表面組裝直接安裝Package （封裝）（封裝）: Chip PackageConnections Made in a Package Attachment of die to package On-package connections Attachment of package to PCBPackage Example: FCBGA Variations of Pac

18、kagesl Attachment of die to packagep Wirebond Peripheral I/O locationp Flip chip, Area Array I/O locationl Attachment of package to PCBp PTH (Pin-Through-Hole), p SMT (Surface Mount Technology)l I/O locationsp Peripheralp Area Arrayl Package Materialsp Plastic,p Ceramicp Thin FilmAttachment of die t

19、o packageAttachment of die to packagelA ring of bondwire attach pads on the periphery of the face of the die. lOn the package, the bondwire lands on package routing. lA bondwire is about 1mil（25.4um） in diameter, 50-500mils （1.27mm-12.7mm) long. lA bondwire acts like an inductor.lThe die is placed f

20、ace down. lSolder balls attach the on-die pads to the surface of the package. lThe die pads are not limited to the periphery.lThe technology is self-aligning because the solder ball surface tension pulls the die pads into alignment with the package pads.Wire bondFlip-chipPros and Cons to Wire-Bond a

21、nd Flip-ChipWire bondFlip-ChipInductanceMuch higher (1-5nH)Much less (.1nH)CrosstalkHigh Virtually none!CostCheap!HighMechanicalGoodPhysical tolerances tightsince must align. ThermalBack of die attached to package for max surface area contact and max heat transfer out. Ugly: thermal coefficients of

22、die and package must be similar otherwise expansion will break it. Cooling hard because die lifted off package by solder balls.Die SizeLimits I/O since pads only around periphery.Die size can be minimized even many I/Os.Wirebond ModelingBall bondBond padChipRouting on PackagePackage dielectric layer

23、Package Substrate(reference plane in this case)A B C DTo approximate by hand: Subdivide the problem into sections for approximation Sections A and D are roughly perpendicular to the plane beneath, so they can be approximated using a simple straight-wire formula.214ln2432ln2pllLrllLooFor round wire,

24、r2 driving chips?CPU 1CPU2ChipsetFull System Modeling Putting Togetherl Multi-drop bus topologies are very common, for example a chipset with multiple processors.l The effect of packaging on such bus topologies is dependent on the package stub length. Modeling of Small StubsZoZoZbTDstubSmall stub( )

25、 treated as lumped C:risestubtTD5 . 0ZoZobstubstubZTDCEffect of Shunt C on RisetimessZZsCZZsC1/)(/)(001001sZsCZZsCT11/)(/)(101001Step Response:sssVL11121)()(121)(/tUetVtLjs 2/0CZ0022222CZCZtrise.Equivalent risetime:U(t)Z0CZ0Z0Z0Note: (1) Vin=1/2 V (voltage division);(2): U(t)1/s in Laplace Transform

26、 domain. Modeling of Long Stubs More VariantsLong stub ( ) modeled as T-line; and Cload modeled as a segment of T-line risestubtTD5 . 0loadbcCZTD ZoZoZbTDstubCloadZoZoZbTDstubTDcZbSimplification based on edge rateEffect of Package: Point to point bus topologyEffect of Package: Multi-drop bus topolog

27、ySmall package stub effect:2)(112)()(2)(/)(/)()(11/)(0000001001001010CjZTCjZCjZCjZZZCjZZCjCjZZCjZZCjcapcapcap002)( 2 . 22 . 2CZCZtedge22inputedgetttsystem%21 9010TTDstubLong package stub effect:Effect of Package: Multi-drop bus topology%21 9010TTDstubLong package stub effect31752550255025/0002002stu

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