ISE中常見(jiàn)WARNING和ERROR及其解決方法

1、WARNING:Route:455-CLKNet:trn_clk_OBUFmayhaveexcessiveskewbecause0CLKpinsand1NON_CLKpinsfailedtorouteusingaCLKtemplate.SolutionThismessageinformstheuserthatsomeloadsontheclocknetarenotclockpins.Therefore,theclocktemplatethatisnormallyusedtoconnectclockpinswillnotbeusedtoconnecttheloads.Adifferentrout

2、ingthatinvolveslocalroutingwillbeused,potentiallyinducingsomeskewontheclocknet.OpeningyourdesigninFPGAEDITORwillallowyoutoseewhatloadsareconnectedtotheclocknet,andthecauseofthewarnings.TheamountofskewonthenetwillbereportedinthePlaceandRoutereport.IftheloadsonthenetshowninFPGAEditorareinaccordwithyou

3、rdesign,theskewreportedinthePARreportisnotcriticalforthedesign,andthetimingconstraintrequirementonthatnetismet,thenthiswarningcanbesafelyignored.實(shí)例原因：在代碼中用到這樣的語(yǔ)句時(shí)（aaeventandaa=T）,aa不是時(shí)鐘信號(hào)，最多只是時(shí)鐘信號(hào)產(chǎn)生的一類周期信號(hào)，aa被作為了另一個(gè)進(jìn)程或模塊的類似周期信號(hào)的作用。（我是在行場(chǎng)信號(hào)發(fā)生器中出現(xiàn)的這樣的問(wèn)題，用產(chǎn)生的行同步信號(hào)（行同步信號(hào)是由全局時(shí)鐘信號(hào)驅(qū)動(dòng)產(chǎn)生的）再去驅(qū)動(dòng)產(chǎn)生場(chǎng)同步信號(hào)，產(chǎn)生的場(chǎng)同步信

4、號(hào)相對(duì)與輸入的全局時(shí)鐘，有一定的傾斜）WARNING:Xst:647-Inputisneverused.orWARNING:Xst:648-Outputisneverused.SolutionThisparticularporthasbeendeclaredinyourHDLdescription,butdoesnotdriveorisnotdrivenbyanyinternallogic.Unusedinputportswillremaininthedesign,buttheywillbecompletelyunconnected.Iftheportisnotintendedtobeused

5、,thismessagecanbesafelyignored.Toavoidthismessage,removeanyloadlessorsourcelesselementsfromyourHDLdescription.Outputportswillremaininthefinalnetlistandwillbedrivenbyalogic0.Toavoidthemessageandtosavetheportresource,removetheunusedoutputportfromyourHDLdescription.實(shí)例原因：一般輸入端口不要預(yù)留，即使不使用，在代碼中定義的輸入端口就一定要

6、有輸入的;而輸出端口不用到的可以用OPEN封上，最常見(jiàn)的是在利用DLL和DCM時(shí),CLK90,CLK180，CLK270等一般不用，在端口連接的時(shí)候都用OPEN封上。ERROR:HDLParsers:3562-pepExtractor.prjline1Expectingvhdorverilogkeyword,foundwork。SolutionThisoccurswhentherearespacesembeddedintheprojectlocation.Abadexampleforprojectlocationwouldbe:C:/DocumentsandSettings/User/exam

7、ple.ise.Agoodexamplefprprojectlocationwouldbe:C:/ISE_tests/example.ise.實(shí)例原因：在ISE9.1的版本里，在行為仿真和使用約束編輯器的時(shí)候會(huì)遇到，主要原因是工程的路徑名里有空格一類的不被要求的非英文字符。ERROR:Xst:2587Portofinstancehasdifferenttypeindefinition.SolutionComparethecomponentdeclarationandinstantiationtothesubmodulethatisinstantiated.Whenthiserroroccurs

8、,thedeclarationmatchestheinstantiation,butdoesnotmatchtheportdeclarationsofthesubmodule.Changeeithertheportdeclarationsinthedeclaration/instantiationpairorthesubmoduleportdeclarationssothattheymatch.Thiserrorisspecifictothetypesofportsinthesubmodule.實(shí)例原因：一般是子模塊宣稱和子模塊的實(shí)體定義中端口的寬度和類型(in,out,inout,buffe

9、r)不匹配造成的。XSTcangenerateverylargelogfilesforcertaindesigns.Insomecases,thegenerationoftheselogfilescanevencauseanincreaseinruntime.HowcanIeliminateorhidecertainfrequentlygeneratedmessages?SolutionForusersofXSTviaProjectNavigatorStartinginISE7.1i,ProjectNavigatorhasthecapabilitytodomessagefilteringfor

10、allXilinxtools.PleaserefertotheProjectNavigatorhelponhowtousethismethod.ForusersofXSTviacommandlineYoucanhidespecificmessagesgeneratedbyXSTattheHDLorLow-LevelSynthesisstepsinspecificsituationsbyusingtheXIL_XST_HIDEMESSAGESenvironmentvariable.Thisenvironmentvariablecanhaveoneofthefollowingvalues:-non

11、e:maximumverbosity.Allmessagesareprintedout.Thisisthedefault.-hdl_level:reduceverbosityduringVHDL/VerilogAnalysisandHDLBasicandAdvancedSynthesis.-low_level:reduceverbosityduringLow-levelSynthesis-hdl_and_low_levels:reduceverbosityatallstagesThefollowingmessagesarehiddenwhenhdl_levelorhdl_and_low_lev

12、elsvaluesarespecifiedfortheXIL_XST_HIDEMESSAGESenvironmentvariable:WARNING:HDLCompilers:38-design.vlinexxMacromy_macroredefinedNOTE:ThismessageisissuedbytheVerilogcompileronly.WARNING:Xst:916-design.vhdlinexx:Delayisignoredforsynthesis.WARNING:Xst:766-design.vhdlinexx:GeneratingaBlackBoxforcomponent

13、comp.InstantiatingcomponentcompfromLibrarylib.Setuser-definedpropertyLOC=X1Y1forinstanceinstinunitblock.Setuser-definedpropertyRLOC=X1Y1forinstanceinstinunitblock.Setuser-definedpropertyINIT=1forinstanceinstinunitblock.Registerreg1equivalenttoreg2hasbeenremoved.Thefollowingmessagesarehiddenwhenlow_l

14、evelorhdl_and_low_levelsvaluesarespecifiedfortheXIL_XST_HIDEMESSAGESenvironmentvariable:WARNING:Xst:382-Registerreg1isequivalenttoreg2.Registerreg1equivalenttoreg2hasbeenremoved.WARNING:Xst:1710-FF/Latchreg(withoutinitvalue)isconstantinblockblock.WARNING:Xst1293-FF/Latchregisconstantinblockblock.WAR

15、NING:Xst:1291-FF/Latchregisunconnectedinblockblock.WARNING:Xst:1426-ThevalueinitoftheFF/Latchreghinderstheconstantcleaningintheblockblock.Youcouldachievebetterresultsbysettingthisinittovalue.實(shí)例原因：在綜合時(shí)，有很多的綜合警告是可以忽略的，以上大致的羅列幾項(xiàng)。WARNING:Xst:737-Foundn-bitlatchforsignal.Thelistingfornisthewidthofthelatc

16、h.Iflatchinferenceisintended,youcansafelyignorethismessage.However,someinefficientcodingstylescanleadtoaccidentallatchinference.Youshouldanalyzeyourcodetoseeifthisresultisintended.Theexamplesbelowillustratehowyoucanavoidlatchinference.實(shí)例原因：一般出現(xiàn)這樣的問(wèn)題都是代碼出現(xiàn)了鎖存器，因避免這樣的代碼寫(xiě)法，電路會(huì)不穩(wěn)定，因利用觸發(fā)器去寄存數(shù)據(jù)在時(shí)鐘沿。Soluti

17、on1IncludeallpossiblecasesinthecasestatementVerilogalways(SELorDIN1orDIN2)begincase(SEL)2b00:DOUT=DIN1+DIN2;2b01:DOUT=DIN1-DIN2;2b10:DOUTDOUTDOUTDOUT=DIN1;endcase;endprocess;ThesetwoexamplescreatelatchesbecausethereisnoprovisionforthecasewhenSEL=11.Toeliminatethelatches,addanotherentrytodealwiththis

18、possibility.Verilog2b11:DOUTDOUT=DIN2;UsingtheDEFAULT(Verilog)orWHENOTHERS(VHDL)clausealwaysworks,butthiscancreateextraneouslogic.Thisisalwaysthesafestmethodology,butmightproducealargerandslowerdesignsinceanyunknownstatehaslogicthatisneededtobringittoaknownstate.Solution2Assigntoallthesameoutputsine

19、achcase.Verilogalways(SELorDIN1orDIN2)begincase(SEL)2b00:DOUT=DIN1+DIN2;2b01:DOUT=DIN1-DIN2;2b10:DOUT=DIN1;2b11:beginDOUT=DIN2;TEMPDOUTDOUTDOUTDOUT=DIN2;TEMP=DIN1;endcase;endprocess;Theseexamplesinferlatchesbecausethe11caseassignstwooutputs,whiletheothersassignonlyone.LookingatthiscasefromTEMPspoint

20、ofview,onlyoneoffourpossiblecasesarespecified,soitisincomplete.Youcanavoidthissituationbyassigningvaluestotheexactsamelistofoutputsforeachcase.Solution3Makesureanyif/elseifstatementshaveaconcludingelseclause:VHDL:process(ge,din)beginif(ge=1)thendout_a=din;elsedout_a=0;-Thisisaconcludingelsestatement

21、.endif;endprocess;Verilog:always(geordin)if(ge)dout_a=din;elsedout_a=1b0;/Thisisaconcludingelsestatement.在不影響電路功能的情況下，要寫(xiě)完整的if-else語(yǔ)句。(對(duì)于時(shí)鐘沿觸發(fā)時(shí)，是不要else的)ERROR:Place:1018-AclockIOB/clockcomponentpairhavebeenfoundthatarenotplacedatanoptimalclockIOB/clocksitepair.Theclockcomponentisplacedatsite.TheIOcomponentisplacedatsite.ThiswillnotallowtheuseofthefastpathbetweentheIOandtheClockbuffer.Ifthissuboptimalconditionisacceptableforthisdesign,youmayusetheCLOCK_DEDICATED_ROUTEconstraintinthe.ucf