外文翻譯--ST7536介紹

ST7536 introduce By Joel HULOUX I- INTRODUCTION TO THE ST7536 The ST7536 is a half duplex synchronous FSK-modem,and has been designed to operate on powerline networks.For a complete communication system, a micro-controller and a powerline-interface (PLI) are needed (see Figure 1).Such a system is able to transmit and receive on 4 different channels with 2 differentdata rates (600 and 1200 baud).The baudrate (BRS) and channel (CHS) selection is made,according to the Table. The ST7536 is a half duplex modem,as it has two operation modes；receive or transmit data.The mode selection is made with a Rx/Tx control input.Data input and output are related to the clock signal；its a synchronous modem. This clock signal is generated by the ST7536.Only a few external components have to be added for full operation of the ST7536:a crystal, four resistors and five capacitors. II- ST7536 DESCRIPTION The ST7536 is a single chip modem；all the electrical circuits needed for a complete modem are inside the chip. The modem is available in 28 pins PLCC (see Figure 2).In transmit mode the Transmit Data (TxD) is sampled on the positive edge of the clock (CLR/T).Then the data enters the FSK modulator. The frequency on which this modulator operates is set by the time base and control logic. In normal operation the multiplexer(MUX) selects the FSK modulator signal to be send to the transmit filter.This filter is a switched capacitor band-pass filter. Thetime base and controllogic uses the Automatic Frequency Control (AFC) to set this filter at the transmit frequency, corresponding to the selected channel.After filtering, the transmitsignal is sent to an Automatic Level Control (ALC).This control is used to overcome problems with line impedance variations. The powerlines on which the modem has to operate, have variations in their line characteristics,which are very frequent and totally unpredictable.The automatic level control uses a feed back signal (ALCI) from the powerline interface to adjust the transmit output (ATO).In receive mode the signal enters the chip on the Receive AnalogInput(RAI). The received signal is filtered in the receive band-pass filter. Its just like the transmit filter,a switched capacitor filter.The automatic frequency control is used to set it on the right frequency. After being amplified the signal is down converted and filtered in the intermediate frequency band-pass filter.The resulting signal is sent to the FSK demodulator. The coupling of the intermediate frequency filter output (IFO) to the FSK DEModulator Input(DEMI) is made by an externalcapacitor which cancelsan even tualoff set voltage. A clock recovery circuit extracts the receive clock (CLR/T) from the demodulated output (RxDEM) of the FSK demodulator. Synchronous received data (RxD) is delivered on the positive edge of the clock.A time base section delivers all the internal clock signals from a crystal oscillator running at 11.0592MHz.The crystal is connected between the XTAL1 and XTAL2 pins.It is also possible to provide directly a clock signal on XTAL1 instead of using a crystal.To debug the chip and test external circuits the ST7536 provides some test options. The transmit band-pass filter can be observed using a direct input on the filter. This input (TxFI) is selected by the multiplexer if TEST4 = 1. The Receive bandpass Filter Output (RxFO) is provided at pin 25.Finally the clock recovery can be observed when TEST1 = 1. In this case the TEST3 input gives a direct input to the clock recovery block. III- ST7536 PIN DESCRIPTION The pin description is not given in numerical order,but the pins are described in relation with their function and consequentlysometimes with other pins. - power supply input - channel selection - crystal oscillator input - AFCF stabilisation - automatic level control input - data input and output - test inputs - IFO/DEMI output/input - transmit output and receive input - Rx/Tx control input - reset input III.1- Power Supply Input - Pin 8 (DGND): Digital ground (0V) - Pin 9 (DVDD): Digital positive supply voltage (+5V) - Pin 18 (DVSS): Digital negative supply voltage (-5V) - Pin 21 (AVSS): Analog negative supply voltage (-5V) - Pin 22 (AGND): Analog ground (0V) - Pin 23 (AVDD): Analog positive supply voltage (+5V) Internally the ST7536 has separated power supplies:The digital andanalog circuit sare separated.Externally the power supplies should be connected together.For decoupling,both the positive and negative supplies are decoupled with 2 capacitors.C6 and C7 decouple the positive,C8 and C9 the negative supplies.For proper operation the digital positive supply voltage should be decoupled with a capacitor(C10)mounted close to Pin9.C6,C8 and C10 are100nF/16Vceramic capacitors,C7 and C9 10uF/16V tant alcapacitors (seeFigure 3). III.2 - Channel Selection - Pin 15 (CHS): Channel selection input - Pin 16 (BRS): Baudrate selection input Both inputs are digital inputs (0/+5V). The ST7536 operates with two bit rates: 600 and 1200 baud. These bit rates are selected with pin 16 (BRS). For both bit rates the ST7536 offers two channels,which are selected with pin 15 (CHS).Alogical”0” is represented by 0V, a”1”by +5V. R1 and R2 are pull-down resistors,creating a logical”0”.Closing a switch gives a”1”.The selection is made according to Table 1. III.3 - Crystal Oscillator Input - Pin 13 (XTAL2): Crystal oscillator output - Pin 14 (XTAL1): Crystal oscillator input The internal crystal oscillator of the ST7536 needs an external crystal. This one should be a 11.0592MHz crystal. Two capacitors (C1 and C2) have to be added for proper operation. They are typically 22pF/10V ceramic capacitors. It is also possible to connect directly a clock signal to the oscillator input, in this case the crystal and the capacitors should be removed.On the application board this option is notused. The ST7536 clock signal is the time reference of the system. III.4 - AFCF Stabilisation - Pin 17 (AFCF) : Automatic frequency control output In the ST7536 an automaticcontrol section adjusts the central frequency of the receive and transmit band-passfilters. The stabilityof this sectionhas to be ensured with an external RC network. III.5 - Automatic Level Control Input - Pin 27 (ALCI): Automatic level control input. The output stage of the transmit path consists of an automatic level control (ALC).It offers the possibility to keep the output voltage of the power amplifier independent of variations of the powerline network. The impedance of these networks can be anywhere in the range of 5-100.If the impedance of the powerline changes,the outputof theamplifier will change.With the ALC input it is possible to correct these output variations. To control the output of the powerline interface a feed-back signal is needed. This signal is sent through an amplifier. The automatic level control can decrease the maximum transmit output in 32 steps of 0.84dB. The gain range is 0dB-26dB. A peak detection is done on the signal presented on the ALC Input and the ALCcompares it to two reference voltages, VT1 (1.87V) and VT2 (2.12V). If max. VALCI VT1 the next gain is increased by 84dB. If VT1 max. VALCI VT2 there is no gain change. If VT2 max. VALCI the next gain is decreased by 0.84dB. The gain of the feed-back amplifier is such that the feed-back signal peak voltage falls between VT1 and VT2. III.6 - Data Input and Output - Pin 5 (RxD): Synchronous receive data output - Pin 6 (CLR/T): Receive and transmit clock - Pin 7 (RxDEM): Demodulated data output - Pin 12 (TxD): Transmit data input The ST7536 is a synchronous modem； data input and output are related to the clock (CLR/T). In transmit mode the ST7536 generates this clock signal. The transmit data are sampled on the positive edge of CLR/T. Therefore the TxD should be valid at that moment.In receive mode the demodulated (receive) data is available at pin 7(RxDEM). A clock recovery circuit extracts the clock signal from the demodulated data and delivers synchronous data (RxD) on the positive edge of CLR/T. On the application board the RxDEM data output is not used. All the data signals from and to the ST7536 (RxD, TxD) are related to the clock (CLR/T) (see Figure 8). III.7 - Test Inputs - Pin 3 (TEST4): Test input,with a”1”on this pin the multiplexer selects thetransmit band-pass filter input(TXFI). - Pin 4 (TEST3): Test input which gives a direct acces to the clock recovery circuit.This input is selected when TEST1=”1”. - Pin 10 (TEST1): Test input,a”1”on this pin cancels the automatic switching from transmit to receive mode, and validates the TEST3 input to the clock recovery circuit. - Pin 11(TEST2): Test input,a”1”on this pin reduces the automatic switching time (from transmit to receive mode) to 1.48ms.On the applicationboard TEST 2/3/4 are not used,and Pins 3, 4, and 11 are thereforeset at 0V.With a switch TEST1 can be set at”0”or”1”.See also the Rx/Tx control input. III.8- IFO/DEMIOutput/Input - Pin 19 (IFO): Intermediate frequency filter output - Pin 20 (DEMI): FSK demodulator input The connection between the intermediate frequency filter output and the FSK demodulator input should be made externally with a capacitor (C5, 1uF/10V). III.9 - Transmit Output and Receive Input - Pin 24 (RAI): Receive analog input - pin 28 (ATO): Analog transmit output Pin 24 is the receive input of the ST7536. The receive output of the powerline interface should be connected to this pin.The maximum input voltageis 2VRMS. The receive sensitivity of the ST7536 is 2mVRMS on channel 1 and 2 (600 baud),and 3mVRMS on channel 3 and 4 (1200 baud).Pin 28 is the transmit output of the ST7536. The transmit input of the powerline interface should be connected to this pin. The ATO output is regulated by the ALCI circuit. The maximum output voltage is 3.5VPP. The second harmonic distortion is about -53dB. III.10 - Rx/Tx Control Input - Pin 1 (Rx/Tx): Receive or transmit mode selection input . The ST7536 is a half duplex modem and has therefore two operation modes: receive and transmit. This mode selection is done with the Rx/Tx input. The transmit mode is selected when Rx/Tx is”0”.If Rx/Tx is held a”0”longer than 3 seconds, the ST7536 switches back to receive mode. To set the ST7536 again in transmit mode, Rx/Tx should be held at”1”for a minimum of 3s before being set to”0”.The carrier activation time is 1msec. To be able to observe the transmit output of the ST7536 on the power line interfacefor a longer time than3 seconds it is possible to use the test 1 Input. If this input is set at”1”the automatic switching is disactivated. Then it is possible to transmit a signal but not to receive. III.11 - Reset Input - Pin 2 (RESET): Logic reset and power-down input When this input is set at” 0”the ST7536 is in power-down mode.All the internal logic is then reset.For normal operation this input should be set at”1”.On the application board this input is controlled by the micro-controller. Technical Data Sheet SSC P300 PL Network Interface Controller Features -Enables Low-cost CEBus compatible products -EIA-600 (CEBus) Data Link Layer services -EIA-600 Physical Layer transceiver -Spread Spectrum Carrier Power Line technology -SPI Host Processor interface -Data Link, Controller, and Monitor modes -Single +5 Volt power supply requirement -20 pin SOIC package Introduction The Intellon SSC P300 PL Network Interface Controller is a highly integrated power line transceiver and channel access interface for implementing CEBus compatible products.The SSC P300 provides the Data Link Layer (DLL) control logic for EIA-600 channel access and communication services, a Spread Spectrum Carrier(SSC) power line transceiver, signal conditioning circuitry, and a serial peripheral interface (SPI) compatible host interface. A minimum of external circuitry is required to connect the SSC P300 to the power line. Superior performance is achieved using the SSC P300 in conjunction with the SSC P111 Media Interface IC. The SSC P300 is used with a host microcontroller to construct CEBus compatible products, and serves as the basic communications element in a variety of low-cost power line networking applications. The inherent reliability of SSC signaling technology and incorporation of basic Data Link functionality combine to provide substantial improvement in network and communication performance over other power line communication methods. The SSC P300 also makes an excellent low cost network interface for twisted pair and DC power systems. A typical CEBus power line node using the SSC P300 is illustrated below. SSC P300 Node Block Diagram VDD DC Supply Voltage -0.3to 7.0V VIN Input Voltage at any Pin VSS-0.3 to VDD+0.3V TSTG Storage Temperature -65 to +150C TL Lead Temperature(Soldering,10 seconds)300C Note: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages. Recommended Operating Conditions VDD DC Supply Voltage 4.5、 5.0、 5.5V FOSC Oscillator Frequency 12 +/- 0.01% MHz TA Operating Temperature -40、 +25、 +85C Humidity non-condensing Electrical Characteristics Conditions:VDD = 4.5 to 5.5 V T=-40 to +85C Symbol Parameter Min Typical Max Units VOH Minimum High-level Output Voltage 2.4V VOL Maximum Low-level Output Voltage (1) 0.4V VIH Minimum High-level Input Voltage 2.0V VIL Maximum Low-level Input Voltage 0.8V Hys Minimum Input hysteresis 350 mV IIL Maximum Input Leakage Current +/-10A vSO SSC Signal Output Voltage (2) 4 VP-P IDD Total Power Supply Current 25 mA Latchup (3) 150 mA Notes: 1. IOL = 2 mA 2. ZL = 2K | 10 pF 3. JEDEC JC -40.2 SSC PL P300 Network Interface Controller SSC P300 Pin Assignments 1 4MHZ 4 MHz clock out 4 MHz clock output available for host microcontroller. 2 CS*Chip select Digital input, active low. Enables serial peripheral interface. 3 VSSD Digital ground Digital ground reference. 4 XIN Crystal input Connected to external crystal to excite the ICs internal oscillator and digital clock. 5 XOUT Crystal output Connected to external crystal to excite the ICs internal oscillator and digital clock. 6 VDDD Digital supply 5.0 VDC +/- 10% digital supply voltage with respect to VSSD. 7 INT* Interrupt Digital output, active low. Attention request to host microcontroller. 8 SCLK SPI data clock Serial peripheral interface clock input from host microcontroller. 9 SDO SPI data out Data output to host microcontroller serial peripheral interface. SDO istristate when CS* is false. 10 SDI SPI data in Data input from host microcontroller serial peripheral interface. 11 TS Tristate Active low digital output signal driven from the same internal signal that enables the output amplifier. 12 RST* Reset Active low digital input. 13 VSSA Analog ground Analog ground reference. 14 SO Signal output Analog signal output. Tristate enabled with internal TS signal. 15 C2 Capacitor 2 Connection for 680pF capacitor to ground. 16 C1 Capacitor 1 Connection for 680pF capacitor to ground. 17 SI Signal input Analog signal input. 18 VDDA Analog supply 5.0 VDC +/- 10% analog supply voltage with respect to VSSA. 19 TP0 Test point 0 Reserved pin for testing. 20 VSSD Digital ground Digital ground reference.SSC PL P300 Network Interface Controller SSC P300 Node Overview The SSC P300 is designed to meet the needs of products requiring EIA-600 compatibility. As the SSC P300 uses fewer interface signals than the SSC P400 does, a lower cost host (microcontroller) may be used. Coupling the lower cost host with the low cost of the SSC P300, an EIA-600 compliance node can be added to cost sensitive products. The SSC P300 can transmit and receive all four Data Link services defined in the EIA-600 standard, which allows the designer to select the best Data Link service for the job.As seen in the block diagram on page 1, a typical node consists of three sections: The first section is the host microprocessor or microcontroller, which is responsible for communicating with the SSC P300 and performing application specific tasks. The second section is the SSC P300 itself. It is responsible for resource intensive. Data Link functions and Physical layer services of the protocol. Specific DLL services include transmission and reception of packets, byte-to-symbol conversion for transmitted packets, symbol-to-byte conversion for received packets, transmit channel access (based on packet priority and EIA-600 access rules), and CRC generation and checking. The last section is the power line analog functions. These functions include: coupling the signal frequencies onto the medium, amplification of the transmitted signal to drive the impedance of the medium, and input filtering of the incoming signal.The host communicates with the SSC P300 by issuing commands. These commands provide for the initialization and verification of the nodes operating mode and addresses, for the transmission and reception of packets, and for the return of status information. In general, the host must provide the following functions in order to utilize the SSC P300: 1. Initialization routine. 2. Routine to write commands out to the chip. 3. Routine to read data from the chip. 4. Interrupt service routine. The SSC P300 can be placed into one of three operating modes:Data Link Layer (DLL) mode, Controller(CON) mode,and Monitor(MON) mode. In the DLL mode, the P300 will manage all address matching, and timer resources.In the CON mode, the P300 converts the incoming signal into bytes.It becomes the responsibility of the host to manage address matching and timer resources. The MON mode monitors the medium. Any packet detected on the medium is passed up to the host regardless of the packets address or type. ST7536介紹 Joel HULOUX著 1、 ST7536 的介紹 ST7536是一個半雙工同步 FSK調(diào)制解調(diào)器 ,并且對于設(shè)計和操作電力線網(wǎng)絡(luò)是很有幫助的。對于一個完整的通信系統(tǒng) ,微型控制器和電力線接口 (PLI)是必要的。這樣系統(tǒng)能在 4種不同頻道上以 2種不同的數(shù)據(jù)率 (600和 1200波特 )傳送和接收信號。波特率 (BRS)和頻道 (CHS)選擇在此時被執(zhí)行。 ST7536是一個半雙工調(diào)制解調(diào)器 ,因為它有二個操作方式，接收或傳送數(shù)據(jù)。模式選擇用Rx/或用 Tx作為控制輸入。數(shù)據(jù)輸入和輸出是與時鐘信號有關(guān)的。它是一個同步調(diào)制解調(diào)器。這個時鐘信號由 ST7536所引起。幾個外在分組都必須增加對 ST7536的進(jìn)行設(shè)置 :一個晶振 , 四個 電阻器和五臺電容器。 2、 ST7536 描述 ST7536是一個具有唯一一個芯片的調(diào)制解調(diào)器；所有電子電路需要有一個完整的調(diào)制解調(diào)器處在芯片里面。調(diào)制解調(diào)器是在 28個串口可利用的 PLCC。傳送數(shù)據(jù)的方式 (TxD)被抽樣在時鐘的正面邊緣 (CLR/T)。然后數(shù)據(jù)進(jìn)入 FSK調(diào)制器。這個調(diào)制器所需的頻率被設(shè)置在時間基準(zhǔn)和控制邏輯上。在正常運(yùn)行多重通道 (MUX)選擇的 FSK調(diào)制器信號是送到傳送過濾器的。過濾器是一臺被交換的電容器帶通濾波器。時間基準(zhǔn)和控制邏輯的用途是所謂的自動頻率控制(AFC)的設(shè)置。這過濾器以傳送頻 率 , 對應(yīng)于選擇的頻道，在過濾以后 ,傳輸信號被送到自動電平控制 (ALC)電路。這種控制的使用是為了克服有線的問題阻抗變異。 調(diào)制解調(diào)器必須運(yùn)用在電力線耦合下來的信號 ,變異的出現(xiàn)是在于他們的線性特征發(fā)生改變 ,有些是非常頻繁而且是完全變化莫測的。自動電平控制使用一個反饋信號 (ALCI) 從電力線接口調(diào)整傳送信號 (ATO)。在接收信號進(jìn)入芯片時分析其輸入的方式 (RAI)。接收的信號通過接收帶通濾波器進(jìn)行過濾。它就像傳送過濾器 , 等效于電容過濾器。自動頻率控制使用設(shè)置它在正確的頻率。在被放大以后信號是在轉(zhuǎn)換和過濾下 通過中頻帶通濾波器。收到的信號寄發(fā)到 FSK解調(diào)器。中頻過濾器輸出信號的聯(lián)結(jié) (IFO)對 FSK 解調(diào)器輸入 (DEMI)由均勻集合電壓做改變。 時鐘補(bǔ)救電路時鐘 (CLR/T)是從被解調(diào)的輸出信號提供的。同步被接收的數(shù)據(jù) (RxD)被設(shè)置在正面時鐘的邊緣。時間基本的部分提供所有內(nèi)部時鐘信號從一臺晶體控制振蕩器提供并運(yùn)行在 11.0592MHz。晶振是運(yùn)行于 XTAL1和 XTAL2 之間。它還可能直接地從 XTAL1提取時鐘信號而不是使用晶振。調(diào)試芯片和測試外部 ST7536提供一些測試選擇。傳送帶通濾波器直接通過過濾器被觀 察。這輸入 (TxFI) 由多重通道選擇在 TEST4=1。接收帶通濾波器輸出信號 (RxFO)被設(shè)置在串口 25。最后時鐘補(bǔ)救可能被設(shè)置在 TEST1=1。 TEST3輸入在這種情況下直接根據(jù)輸入時鐘設(shè)置。 3、 ST7536 PIN 描述 串口的描述不需要數(shù)字次序 ,但串口在與其他串口之間的聯(lián)系被描述。 - 電源輸入 - 頻道選擇 - 晶體控制振蕩器輸入 - AFCF平穩(wěn) - 自動電平控制輸入 - 數(shù)據(jù)輸入和輸出 - 測試輸入 - IFO/DEMI輸出輸入 - 傳送輸出和接收輸入 - Rx/Tx控制輸入 - 重新設(shè)置輸 入 3.1 電源輸入 - Pin 8 (DGND): 數(shù)字式接地 (0V) - Pin 9 (DVDD): 數(shù)字式正極供應(yīng) 電壓 (+5V) - Pin 18 (DVSS): 數(shù)字式負(fù)極供應(yīng) 電壓 (-5V) - Pin 21 (AVSS): 模式負(fù)極供應(yīng) 電壓 (-5V) - Pin 22 (AGND): 模式接地 (0V) - Pin 23 (AVDD): 模式正極供應(yīng)電壓 (+5V) ST7536內(nèi)部分離了電源 :數(shù)字式分析電路被分離。外部電源應(yīng)該一起被連接。正極和負(fù)極供應(yīng)與 2 臺電容器分離。 C6 和 C7 由正極供應(yīng) ,C8 和 C9 負(fù)性供應(yīng)。適當(dāng)?shù)牟僮鲾?shù)字式正極電源電壓應(yīng)該被分離。 C6,C8和 C10是 100nF/16V 的電容器 ,C7 和 C9 是 10mF/16的電容器。 3.2 頻道的選擇 PIN15（ CHS）：頻道選擇輸入 PIN16（ BRS）：波特率選擇輸入 以上的兩種輸入都是數(shù)字輸入（ 0/+5V）。這個 ST7536設(shè)置在兩種比特率上：（ 600和1200BAUD）。這些比特率是由 PIN16（ BRS）來選擇的。對于兩種比特率 ST7536通過 PIN15提供兩種頻道。非邏輯 0通過 0V來描述，而非邏輯 1是通過 +5V來描述的。 R1和 R2是被電阻器來隔離的，創(chuàng)造一個邏輯 0，而關(guān)閉給予的非邏輯 1。 3.3 晶體振蕩器的輸入 Pin 13(XTAL2):晶體振蕩器輸出 Pin 14（ XTAL1） :晶體振蕩器輸入 國內(nèi)的 ST7536晶體振蕩器需要一個外部的晶振。它需要一個 11.0592MHZ晶體。電容器（ C1和 C2）需要另外合適的設(shè)置。它們是具有代表性的瓷介電容器。如果晶體和電容器被分離它可能直接連接一個時鐘信號到振蕩器的輸入?；谶@種需求這種選擇是不被使用的。這種ST7536時鐘信號是對系統(tǒng)時間的提及。 3.4 AFCF的描述 PIN 17（ AFCF）：自動頻率控制的輸出。在 ST7536自動控制部件會調(diào)整接收和傳輸?shù)倪厧盘柕闹行念l率。這種部件的穩(wěn)定性必須由一個外部的 RC網(wǎng)絡(luò)來保證 。 3.5 自動電平控制輸入 - Pin 27(ALCI): 自動電平控制輸入。傳送通路的輸出階段包括自動電平控制 (ALC)。它提供保留功率放大器的輸出電壓的獨(dú)立電力線網(wǎng)絡(luò)變異的可能性。這些網(wǎng)絡(luò)阻抗可能是任何在范圍的 5-100W。如果電力線的阻抗改變 ,輸出電壓則變動。對于 ALC的輸入根據(jù)輸出的變化范圍而改變。控制電力線的輸出連接的反饋信號是需要的。這個信號被送往自動增 益控制放大器。 自動電平控制能減少最大傳送輸出信號值在 32步每 0.84dB。增益范圍是 0dB 到 -26dB。高峰檢測是對于在 ALC上的現(xiàn)值信號輸入和 ALC來比較兩種電壓范圍。 VT1(1.87V)與 VT2(2.12V)。 如果最大。 VALCIVT1下增益被增加 0.84dB。 如果 VT1最大。 VALCIVT2增益是沒有改變。 如果 VT2最大。 VALCI下增益被減少 0.84dB。 反饋放大器的增益是這樣，反饋信號峰頂電壓下跌到 VT1與 VT2之間 3.6 數(shù)據(jù)輸入和輸出 - Pin 5 (RxD): 同步接 收數(shù)據(jù)輸出信號 - Pin 6 (CLR/T): 接收和傳送時鐘 - Pin 7 (RxDEM): 被解調(diào)的數(shù)據(jù)輸出 - Pin 12 (TxD): 傳送數(shù)據(jù)輸入 ST7536是一個同步調(diào)制解調(diào)器；數(shù)據(jù)輸入和輸出與時鐘有關(guān) (CLR/T)。在傳送方式下ST7536產(chǎn)生這個時鐘信號。傳送數(shù)據(jù)被抽樣在 CLR/正面邊緣 T。所以 TxD應(yīng)該在那片刻是有根據(jù)的。在接收被解調(diào)的方式 (接受 )數(shù)據(jù)是可利用的在串口 7 (RxDEM)。 時鐘補(bǔ)救電路從被解調(diào)的數(shù)據(jù)提取時鐘信號和提供同步數(shù)據(jù) (RxD)基于 CLR/ 正面邊緣 T。在應(yīng)用 模式 RxDEM數(shù)據(jù)輸出沒被使用。所有數(shù)據(jù)信號對于 ST7536(RxD,TxD)是與時鐘有關(guān)的（ CLR/T） 。 3.7 測試輸入 - Pin 3 (TEST4): 測試輸入 ,與在這個串口多重通道選擇的帶通濾波器輸入 (TXFI)。 - Pin 4 (TEST3): 測試給直接時鐘補(bǔ)償電路的輸入。這輸入被選擇 TEST1。 - Pin 10 (TEST1): 測試輸入 ,在這個串口取消自動開關(guān)從傳送接收方式 , 并且確認(rèn) TEST被輸入到時鐘補(bǔ)償電路。 - Pin 11 (TEST2): 測試輸入 ,在這個串口使自動開關(guān)時 間降低 (從傳送對接收方式 )到1.48ms。在應(yīng)用模式測試 2/3/4不被使用 ,并且串口 3,4,11是設(shè)置在 0。以開關(guān) TEST1可能被設(shè)置在 0或 1。 3.8 IFO/DEMI輸出 / 輸入 - Pin 19 (IFO):中頻過濾器輸出 - Pin 20 (DEMI):FSK解調(diào)器輸入 連接在中頻過濾器輸出和 FSK解調(diào)器輸入之間，如果用電容器 (C5接地 , 1mF/10V) 。 3.9 傳送輸出和接收輸入 - Pin 24 (RAI): 模擬接收輸入 - Pin28 (ATO): 模擬傳送輸出 Pin 24是 ST7536的接受輸入。電力線接口的接收輸出應(yīng)該是連接到這個串口。最大輸入電壓 2V。 ST7536的接收敏感性是 2mV在頻道 1和 2 (600 波特 ), 并且 3mV在頻道 3和 4(1200 波特 )。 Pin 28是 ST7536的傳送輸出。電力線接口的傳送輸入應(yīng)該被連接到這個串口。 ATO輸出由 ALCI電路調(diào)控。最大輸出電壓是 3.5VPP。第二個泛音畸變是 -53dB 。 3.10 Rx/Tx控制輸入 - Pin 1 (Rx/Tx):接收或傳送模式選擇輸入。 ST7536是一個半雙工調(diào)制解調(diào)器和有二個操作方式 :接收和傳送。這個模式 選擇完成與 Rx/Tx輸入。傳送方式被選擇當(dāng) Rx/Tx是 0。如果Rx/Tx選擇 0比 3 秒更長 ,ST7536開關(guān)回到接收方式。設(shè)置 ST7536在重新傳送方式 , Rx/Tx 應(yīng)該選擇在 1為 3ms為最小值在被設(shè)置在 0之前。載體活化作用時間是 1ms。能觀察到 ST7536的傳送輸出比輸電線更久的時間。支持它的接口是可能使用測試 1被輸入。如果這輸入被設(shè)置在 1，自動開關(guān)是不可用的。然后它是可能傳送信號但不接收。 3.11 重新設(shè)置輸入 - Pin 2(重新設(shè)置 ):邏輯重新設(shè)置和降低輸入電壓。這輸入被設(shè)置在 ST7536是在“ 0”降壓方式。所有內(nèi)部邏輯然后被重新設(shè)置。為正常運(yùn)行這輸入應(yīng)該被設(shè)置在“ 1”。應(yīng)用模式的輸入由微型控制器控制。 SSC P300 PL網(wǎng)絡(luò)接口控制器特點 . 使用便宜的 CEBus2O兼容產(chǎn)品 . EIA-600(CEBus)數(shù)據(jù)鏈路層服務(wù) . EIA-600物理層收發(fā)器 . 擴(kuò)展頻譜 Carrier5a輸電線技術(shù) . SPI主處理器接