芯片封裝系統(tǒng)信號完整性協(xié)同分析課件

1、Chip-Package-System(CPS) Signal Integrity Co-AnalysisAgenda2 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017Traditional Industry Trend for Memory Interface Performance CheckANSYS Chip-Package-System Signal Integrity SolutionsDetail Flow Demonstration based on DDR DesignTraditional Performance Check of

2、DDRPHY ProviderManufacturing & MeasurementDesign multiple test IPs with required functions before mass production3 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017Select IP with the best performanceNo IP meeting target performance,needs tremendous effort for root-causing,fixing designLate problem detect

3、ionCost Driven, Long TATThe Higher Performance, the more difficult release products on time Shadow area to SoC chip maker using 3rd part DDRPHYSimulation based Performance Checking Solution is necessaryTraditional System Level Signal IntegrityDirect connection btw IO and PKG without on-die PDNGenera

4、lly consider only signal networks onpackageCant consider power-to-signal coupling Power supply noise induced delayIBIS or TransistorAccuracy Loss due to insufficient data, high probability of under design4 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017Traditional IO Model for DDR Timing AnalysisIBISSi

5、mplestFastest SimulationEasy to HandleConstant delay modelIndependent of supply voltageGlitch, non-convergenceTransistorMost AccurateGreatly longer simulation timeCant full bankanalysis due to capacityIdeal Chip Model isFaster than transistorFull Bank CapacityAs accurate as transistorIncluding IO ci

6、rcuit function and intrinsic parasitic inside IO circuitIncluding Chip Layout(IO/Core PDN), IO decap cell5 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017Chip Signal Model(CSM) for DDR Timing AnalysisIncluding RDL, on-die de-capsMultiple power domainsPer pad/bump broadband modelCompact model enables fa

7、st simulation in spiceCore PDNIOPDNCIOM(Chip IO Model)Non-linear device I/O buffer macro-modelSpice-level accuracy with full I/O bank capacityCaptures impact of P/G noise on signalLoad independentLayout and circuit IP encryptionAlso IBIS 5.0 Generation availableChip Signal ModelCdevESRIntrinsic capa

8、citance extraction of IO Cell6 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017Performance of CIOM and CSMCIOM enables faster and accurate analysis!CSM Measurement, biasedMeasurement, unbiasedCorrelation CSM vs. MeasurementComparison Xtor vs. CIOM vs. IBISCSM is well correlated with system level measure

9、ment7 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017IBIS/Xtor/CIOMOn-chip PDNIntrinsic Cap of IOChip Model Creation for Signal IntegrityChannel Connection & AnalysisCPS Signal Integrity for Chip DesignerAnsys Chip Signal ModelingJEDEC Timing AnalysisPG Noise AnalysisJitter AnalysisPackage/Board in SIw

10、aveRLCG/S-parameterFor IO CellCharacterizationIO Physical Design(GDS/LEF/DEF)IO Spice Netlist8 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017. Enables to predict power/signal Integrity performance check and optimization of DDRPHY. This flow is feasible to package designer who can get chip design infoC

11、PS Signal Integrity for Package DesignerIBIS/Xtor/CIOMOn-chip PDNIntrinsic Cap of IOChip Model Creation for Signal IntegrityChannel Connection & AnalysisJEDEC Timing AnalysisPG Noise AnalysisJitter AnalysisPackage/Board in SIwaveRLCG/S-parameter. Enables package/system designer to do full bank PDN a

12、ware signal integrity analysis. Prevent under/over design due to CSM which has all chip level infoAnsys Chip Signal Modeling9 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017Demo Video: Extract Parasitic of Board PDN via SIwave- CPA10 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017ANSYS Chip Signal Modelin

13、gChip Model generation for DDR timing and EMIChip & System level signal Integrity simulationTarget User: Package designer, Chip DDRPHY orIO designerValidation includes JEDEC compatible timing, noise, jitter, slew reporting covering single ended and differential type IOsCustomized 3DIC, HBM, WLP(Wafe

14、r Level Package) target CSM generation & validationANSYS CSMIO model (CIOM/IBIS/Xtor) generationOn-die PDN modelingModel Validation through system level analysisAdvanced CSM for System level EMI analysisIO-CPMgenerationChip Signal Model generation11 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017ANSYS

15、CSM GUI OverviewCIOM Generation and ValidationDecap ModelingOn-die PDN parasitic extractionCSM Creation & Channel Connection for ValidationCSM Validation through system level analysisJitter Analysis based on Jedec Spec12 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017Chip Signal Model Creation and Vali

16、dation FlowCIOM Generation and ValidationIO Decap ModelingParasitic Extraction and Power IntegrityAnalysis of on-chip PDNCSM(Chip Signal Model) CreationSimulation env. set up for CSM validation1234513 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017What-if analysis for DDRPHY IO/Decap OptimizationIO/Dec

17、ap/Core Instance can be newly defined or added;User-defined cell instances are placed in DDRPHY.IO InstanceCore Instance14 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017Decap InstanceEnables to generate various types of CSM withdifferent optimization case;User can do performance check through channel

18、simulation and select the best case.Demon Video: CSM Model Creation of DDR Design15 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017Channel Connection & Auto Simulation Test bench CreationCSM and all parasitic models from SIwave enables auto electrical connection between driver dies, Package and Board t

19、o receiver through CPP(Chip Package Protocol) header16 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017New Virtual Compliance GUI OverviewEach report cell can pop-up a waveform viewer windowRight click menu can export HTML format report.Report list windowRight clickmenuCompliance test windowWaveform viewerWindowMessage windowTCL command window1217 2017 ANSYS, Inc.August 3, 2017ANSYS UGM 2017Reporting Tables OverviewVirtual Compliance ToolkitSelf Del