序列檢測(cè)器的設(shè)計(jì) 實(shí)驗(yàn)報(bào)告

1、EDA實(shí)驗(yàn)報(bào)告書 姓名xxx 學(xué)號(hào)xxxxxxx 實(shí)驗(yàn)時(shí)間課題名稱序列檢測(cè)器的設(shè)計(jì)實(shí)驗(yàn)?zāi)康?.用狀態(tài)機(jī)實(shí)現(xiàn)序列檢測(cè)器的設(shè)計(jì)2.了解一般狀態(tài)機(jī)的設(shè)計(jì)與應(yīng)用設(shè)計(jì)要求1.采用VHDL語言設(shè)計(jì)序列檢測(cè)器，具體要求如下：（1）檢測(cè)序列為“10101110”。該序列從左到右依次進(jìn)入檢測(cè)器，如果檢測(cè)到完整序列，檢測(cè)器輸出為1，反之輸出為0。（2）利用Quatus II軟件生成狀態(tài)轉(zhuǎn)移圖。（3）對(duì)該檢測(cè)器進(jìn)行仿真，得到仿真波形。2.采用狀態(tài)圖編輯方法設(shè)計(jì)序列檢測(cè)器，檢測(cè)序列為“11010101”。具體要求為（1）對(duì)電路進(jìn)行仿真，得到仿真波形。（2）將該電路圖轉(zhuǎn)化成VHDL語言形式。設(shè)計(jì)思路序列檢測(cè)器可用于檢測(cè)

2、一組或多組由二進(jìn)制碼組成的脈沖序列信號(hào)，當(dāng)序列檢測(cè)器連續(xù)收到一組串行二進(jìn)制碼后，如果這組碼與檢測(cè)器中預(yù)先設(shè)置的碼相同,則輸出為1，否則輸出為0.由于這種檢測(cè)的關(guān)鍵在于正確碼的收到必須是連續(xù)的，這就要求檢測(cè)器必須記住前一次的正確碼及正確序列，直到在連續(xù)的檢測(cè)中所收到的每一位碼都與預(yù)置數(shù)的對(duì)應(yīng)碼相同。在檢測(cè)過程中，任何一位不相等都將回到初始狀態(tài)重新檢測(cè)。設(shè)計(jì)原理圖及源程序LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY AA ISPORT ( CLK ,DIN,RST : IN STD_LOGIC; SOUT : OUT STD_LOGIC;END

3、AA;ARCHITECTURE behav OF AA IS TYPE states IS (s0, s1, s2, s3,s4,s5,s6,s7,s8); SIGNAL ST,NST : states :=s0 ; BEGIN COM : PROCESS(ST,DIN) BEGIN CASE ST IS WHEN s0 = IF DIN = 1 THEN NST = s1;ELSE NST IF DIN = 0 THEN NST = s2;ELSE NST IF DIN = 1 THEN NST = s3;ELSE NST IF DIN = 0 THEN NST = s4;ELSE NST

4、IF DIN = 1 THEN NST = s5;ELSE NST IF DIN = 1 THEN NST = s6;ELSE NST IF DIN = 1 THEN NST = s7;ELSE NST IF DIN = 0 THEN NST = s8;ELSE NST IF DIN = 0 THEN NST = s2;ELSE NST NST = st0; END CASE ; END PROCESS; REG: PROCESS (CLK,RST) BEGIN IF RST=1 THEN ST=s0; ELSIF ( CLKEVENT AND CLK=1) THEN ST=NST; END

5、IF; END PROCESS REG; SOUT=1WHEN ST=s8 ELSE 0 ;END behav;仿真波形圖實(shí)驗(yàn)結(jié)果LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY SM1 IS PORT ( clock : IN STD_LOGIC; reset : IN STD_LOGIC := 0; input1 : IN STD_LOGIC := 0; input2 : IN STD_LOGIC := 0; output1 : OUT STD_LOGIC );END SM1;ARCHITECTURE BEHAVIOR OF SM1 IS TY

6、PE type_fstate IS (st1,st2,st3,st4,st5,st6,st7,st8,st0); SIGNAL fstate : type_fstate; SIGNAL reg_fstate : type_fstate;BEGIN PROCESS (clock,reset,reg_fstate) BEGIN IF (reset=1) THEN fstate = st1; ELSIF (clock=1 AND clockevent) THEN fstate = reg_fstate; END IF; END PROCESS; PROCESS (fstate,input1,inpu

7、t2) BEGIN output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st2; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st3; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st4; ELSE reg_fstate = st0; END IF; outpu

8、t1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st5; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st6; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st7; ELSE reg_fstate = st0; END IF; output1 IF (input1 =

9、 1) AND (input2 = 1) THEN reg_fstate = st8; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st3; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st1; ELSE reg_fstate = st0; END IF; output1 output1 = X; report Reach undefined state; END CASE; END PROCESS;END BEHAVIOR;問題討論1. 利用序列檢測(cè)器設(shè)計(jì)簡(jiǎn)易數(shù)字密碼鎖。先輸入一個(gè)密碼，然后在程序中設(shè)定一個(gè)你