EDA實驗報告終極版.doc

_學(xué)院 專業(yè) 班、學(xué)號 姓名 協(xié)作者_(dá) 教師評定_實驗題目_基于Libero的數(shù)字邏輯設(shè)計仿真及驗證實驗_1、 熟悉EDA工具的使用；仿真基本門電路。2、 仿真組合邏輯電路。3、 仿真時序邏輯電路。4、 基本門電路、組合電路和時序電路的程序燒錄及驗證。5、 數(shù)字邏輯綜合設(shè)計仿真及驗證。實驗報告1、基本門電路一、實驗?zāi)康?、了解基于Verilog的基本門電路的設(shè)計及其驗證。2、熟悉利用EDA工具進(jìn)行設(shè)計及仿真的流程。3、學(xué)習(xí)針對實際門電路芯片74HC00、74HC02、74HC04、74HC08、74HC32、74HC86進(jìn)行VerilogHDL設(shè)計的方法。二、實驗環(huán)境Libero仿真軟件。三、實驗內(nèi)容1、掌握Libero軟件的使用方法。2、進(jìn)行針對74系列基本門電路的設(shè)計，并完成相應(yīng)的仿真實驗。3、參考教材中相應(yīng)章節(jié)的設(shè)計代碼、測試平臺代碼（可自行編程），完成74HC00、74HC02、74HC04、74HC08、74HC32、74HC86相應(yīng)的設(shè)計、綜合及仿真。4、提交針對74HC00、74HC02、74HC04、74HC08、74HC32、74HC86（任選一個）的綜合結(jié)果，以及相應(yīng)的仿真結(jié)果。四、實驗結(jié)果和數(shù)據(jù)處理1、所有模塊及測試平臺代碼清單/74HC00代碼-與非/ 74HC00.vmodule HC00(A, B, Y); input 3:0 A, B; output3:0 Y; assign Y = (A&B);endmodule/74HC00測試平臺代碼/ test_00.vtimescale 1ns/1nsmodule test_00; reg 3:0 a,b; wire 3:0 y; HC00 u(a, b, y); initial begin a = 4b0000;b = 4b0001; #10 b = b1;/0010 #10 b = b1;/0100 #10 b = b1;/1000 a = 4b1111;b = 4b0001; #10 b = b1; #10 b = b1; #10 b = b1; endendmodule/74HC02代碼-或非/ 74HC02.vmodule HC02(A, B, Y); input 3:0 A, B; output3:0Y; assignY = (A|B);endmodule/74HC02測試平臺代碼/ test_02.vtimescale 1ns/1nsmodule test_02; reg3:0 a,b,c; wire 3:0 y; HC02 u(a, b, y); initial begin a = 4b1111;c = 4b0001; b = c;c = c1; #10 b = c;c = c1; #10 b = c;c = c1; #10 b = c; a = 4b0000;c = 4b0001; b = c;c = c1; #10 b = c;c = c1; #10 b = c;c = c1; #10 b = c; endendmodule/74HC04代碼-非/ 74HC04.vmodule HC04(A, Y); input3:0 A; output3:0Y; assignY = A;endmodule/74HC04測試平臺代碼/ test_04.vtimescale 1ns/1nsmodule test_04; reg3:0 a; wire 3:0 y; HC04 u (a, y); initial begin a = 4b0001; #10 a = a1; #10 a = a1; #10 a = a1; endendmodule/74HC08代碼-與/ 74HC08.vmodule HC08(A, B, Y);input3:0 A, B;output3:0Y;assignY = A&B;endmodule/74HC08測試平臺代碼/ test_08.vtimescale 1ns/1nsmodule test_08; reg3:0 a,b; wire 3:0 y; HC00 u(a, b, y); initial begin a = 4b0000;b = 4b0001; #10 b = b1; #10 b = b1; #10 b = b1; a = 4b1111;b = 4b0001; #10 b = b1; #10 b = b1; #10 b = b1; endendmodule/74HC32代碼-或/74HC32.vmodule HC32(A, B, Y);input 3:0 A, B;output3:0Y;assignY = A|B;endmodule/74HC32測試平臺代碼/ test_32.vtimescale 1ns/1nsmodule test_32; reg3:0 a,b,c; wire 3:0 y; HC02 u(a, b, y); initial begin a = 4b1111;c = 4b0001; b = c;c = c1; #10 b = c;c = c1; #10 b = c;c = c1; #10 b = c;a = 4b0000;c = 4b0001; b = c;c = c1; #10 b = c;c = c1; #10 b = c;c = c1; #10 b = c; endendmodule/74HC86代碼-異或module HC86(A, B, Y);input3:0 A, B;output3:0Y;assignY = AB;endmodule/74HC86測試平臺代碼/ test_86.vtimescale 1ns/1nsmodule test_86; reg3:0 a, b; wire 3:0 y; HC86 u (a, b, y); initial begin a = 4b0000;b = 4b0001; #10 b = b1; #10 b = b1; #10 b = b1;#10 a = 4b1111;b = 4b0001; #10 b = b1; #10 b = b1; #10 b = b1; endendmodule2、第一次仿真結(jié)果（任選一個門，請注明，插入截圖，下同）。（將波形窗口背景設(shè)為白色，調(diào)整窗口至合適大小，使波形能完整顯示，對窗口截圖。后面實驗中的仿真使用相同方法處理）3、綜合結(jié)果（截圖）。（將相關(guān)窗口調(diào)至合適大小，使RTL圖能完整顯示，對窗口截圖，后面實驗中的綜合使用相同方法處理）4、第二次仿真結(jié)果（綜合后）（截圖）?；卮疠敵鲂盘柺欠裼醒舆t，延遲時間約為多少？輸出信號有延遲，延遲時間約為0.3ns5、第三次仿真結(jié)果（布局布線后）（截圖）。回答輸出信號是否有延遲，延遲時間約為多少？分析是否有出現(xiàn)競爭冒險。輸出信號有延遲，延遲時間約為3ns,沒有出現(xiàn)競爭冒險。2、組合邏輯電路一、實驗?zāi)康?、了解基于Verilog的組合邏輯電路的設(shè)計及其驗證。2、熟悉利用EDA工具進(jìn)行設(shè)計及仿真的流程。3、學(xué)習(xí)針對實際組合邏輯電路芯片74HC148、74HC138、74HC153、74HC85、74HC283、74HC4511進(jìn)行VerilogHDL設(shè)計的方法。二、實驗環(huán)境Libero仿真軟件。三、實驗內(nèi)容1、掌握Libero軟件的使用方法。2、進(jìn)行針對74系列基本組合邏輯電路的設(shè)計，并完成相應(yīng)的仿真實驗。3、參考教材中相應(yīng)章節(jié)的設(shè)計代碼、測試平臺代碼（可自行編程），完成74HC148、74HC138、74HC153、74HC85、74HC283、74HC4511相應(yīng)的設(shè)計、綜合及仿真。4、74HC85測試平臺的測試數(shù)據(jù)要求：進(jìn)行比較的A、B兩數(shù)，分別為本人學(xué)號的末兩位，如“89”，則A數(shù)為“1000”，B數(shù)為“1001”。若兩數(shù)相等，需考慮級聯(lián)輸入（級聯(lián)輸入的各種取值情況均需包括）；若兩數(shù)不等，則需增加一對取值情況，驗證A、B相等時的比較結(jié)果。5、74HC4511設(shè)計成擴(kuò)展型的，即能顯示數(shù)字09、字母af。6、提交針對74HC148、74HC138、74HC153、74HC85、74HC283、74HC4511（任選一個）的綜合結(jié)果，以及相應(yīng)的仿真結(jié)果。四、實驗結(jié)果和數(shù)據(jù)處理1、所有模塊及測試平臺代碼清單/74HC148代碼/ 74HC148.vmodule HC148(EI, In, Out, EO, GS);inputEI;input7:0In;output2:0Out;outputEO, GS;reg2:0Out;regEO, GS;intergerI;always (EI or In)if(EI)beginOut = 3b111; EO = 1;GS = 1;endelseif( In = 8b11111111 )beginOut = 3b111;EO = 0;GS = 1;endelsebeginfor(I = 0;I 8; I = I + 1)beginif( InI)beginOut = I;EO = 1; GS = 0;endendendendmodule/74HC148測試平臺代碼/ test_148.vtimescale 1ns/1nsmodule test_148;reg ei;reg 7:0turn;wire 7:0in = turn;wire 2:0out;wire eo,gs;HC148 u(ei, in, out, eo, gs);initialbeginei = 1;turn = 8b1;repeat(8)#10 turn = turn1;ei = 0;turn = 8b1;repeat(8)#10 turn = turn1;endendmodule/74HC138代碼/ 74HC138.vmodule decoder3_8_1(DataIn,Enable,Eq);input 2:0 DataIn;input Enable;output 7:0 Eq;reg 7:0 Eq;wire2:0 DataIn;integer I;always (DataIn or Enable)beginif(Enable) Eq=0; else for(I=0;I=7;I=I+1) if(DataIn=I) EqI=1; else EqI=0;endendmodule/74HC138測試平臺代碼/ test_138.vtimescale 1ns/1nsmodule test_138;wire 2:0 out;reg 7:0 in;reg 2:0 ei;HC138 u(out, in, ei);task circle;beginin = 0;repeat(8)#10 in = in + 1;endendtaskinitial beginei = 1;circle(); ei = 0;circle(); ei = 2; repeat(6) begin circle(); #10 ei = ei + 1; endendendmodule/74HC153代碼/ 74HC153.vmodule HC153(DateOut, DateIn, Sel, Enable);input3:0DateIn;input1:0Sel;inputEnable;output regDateOut;always (Enable or Sel or DateIn)if(Enable)DateOut = 0;elseDateOut = DateInSel;endmodule/74HC153測試平臺代碼/ test_153.vtimescale 1ns/1nsmodule test_153();wire out;reg 3:0in;reg 1:0sel;reg ei;HC153 u(out, in, sel, ei);initialbegin ei = 0;sel = 0;in = 4b1010;repeat(4)#10 sel = sel +1; ei = 1;sel = 0;in = 4b1010;repeat(4)#10 sel = sel +1;endendmodule/74HC85代碼/ 74HC85.vmodule HC85(DateA, DateB, Cas, Q);input3:0 DateA, DateB;input2:0Cas;output reg2:0Q;intergerI;always (DateA or DateB or Cas)beginif(DateA=DateB)beginif(Cas1)Q = 3b010; else if(Cas=3b000)Q = 3b101; else if(Cas=3b101)Q = 3b000;elseQ = Cas; endelsebeginfor(I=0;IDateBI)Q = 3b100;else if(DateAIDateBI)Q = 3b001;endendendmodule/74HC85測試平臺代碼/ test_85.vtimescale 1ns/1nsmodule test_85;reg 3:0 a,b;reg 2:0 cas;wire 2:0 res;HC85 u(a, b, cas, res);task cascade_input;begin#0 cas = 0;#10 cas = 1;#10 cas = 3b100;#10 cas = 3b101;#10 cas = 3b010;#10 cas = 3b011;#10 cas = 3b110;#10 cas = 3b111;#10;endendtaskinitialbegina = 4d9;b = a;cascade_input();b = 4d7;cascade_input();endendmodule/74HC283代碼/ 74HC283.vmodule HC283(DateA, DateB, Cin, Sum, Cout);input3:0 DateA, DateB;inputCin;output3:0 Sum;outputCout;reg4:0Buf;assign Cout,Sum = Buf;always (DateA or DateB or Cin)Buf = DateA + DateB + Cin + 5d0;endmodule/74HC283測試平臺代碼/ test_283.vtimescale 1ns/1nsmodule test_283;reg 3:0 a, b;reg in;wire 3:0sum;wire out;interger I;HC283 u(a, b, in, sum, out);task accumulate;begin a = 4b0100;for(I=0;I16;I=I+1)beginb = I;#10;endendtaskinitialbeginin = 0; accumulate();in = 1;accumulate();endendmodule/74HC4511代碼/ 74HC4511.vmodule HC4511(DateOut, DateIn, LE, BL_N, LT_N);output7:0DateOut;input3:0DateIn;inputLE, BL_N, LT_N;reg7:0Buf;assignDateOut = Buf;always (DateIn or LE or BL_N or LT_N)beginif(!LT_N)Buf = 8b11111111;else if(!BL_N)Buf = 8b0000000;else if(LE)Buf = Buf;elsecase(DateIn)4d0:Buf = 8b00111111;4d1:Buf = 8b00000110;4d2:Buf = 8b01011011;4d3:Buf = 8b01001111;4d4:Buf = 8b01100110;4d5:Buf = 8b01101101;4d6:Buf = 8b01111101;4d7:Buf = 8b00000111;4d8:Buf = 8b01111111;4d9:Buf = 8b01101111; 4ha:Buf = 8b01110111;4hb:Buf = 8b01111100;4hc:Buf = 8b00111001;4hd:Buf = 8b01011110;4he:Buf = 8b01111001;4hf:Buf = 8b01110001;default:;endcaseend2、第一次仿真結(jié)果（任選一個模塊，請注明）74HC1483、綜合結(jié)果4、第二次仿真結(jié)果（綜合后）?；卮疠敵鲂盘柺欠裼醒舆t，延遲時間約為多少？輸出信號有延遲，延遲時間約為0.5ns5、第三次仿真結(jié)果（布局布線后）?；卮疠敵鲂盘柺欠裼醒舆t，延遲時間約為多少？分析是否有出現(xiàn)競爭冒險。輸出信號有延遲，延遲時間約為5.2ns，出現(xiàn)了競爭冒險。3、時序邏輯電路一、實驗?zāi)康?、了解基于Verilog的時序邏輯電路的設(shè)計及其驗證。2、熟悉利用EDA工具進(jìn)行設(shè)計及仿真的流程。3、學(xué)習(xí)針對實際時序邏輯電路芯片74HC74、74HC112、74HC194、74HC161進(jìn)行VerilogHDL設(shè)計的方法。二、實驗環(huán)境Libero仿真軟件。三、實驗內(nèi)容1、熟練掌握Libero軟件的使用方法。2、進(jìn)行針對74系列時序邏輯電路的設(shè)計，并完成相應(yīng)的仿真實驗。3、參考教材中相應(yīng)章節(jié)的設(shè)計代碼、測試平臺代碼（可自行編程），完成74HC74、74HC112、74HC161、74HC194相應(yīng)的設(shè)計、綜合及仿真。4、提交針對74HC74、74HC112、74HC161、74HC194（任選一個）的綜合結(jié)果，以及相應(yīng)的仿真結(jié)果。四、實驗結(jié)果和數(shù)據(jù)處理1、所有模塊及測試平臺代碼清單/74HC74代碼/ 74HC74.vmodule HC74(Set_N, Rst_N, Clk, D, Q, Qn);inputSet_N, Rst_N, Clk, D;outputQ, Qn;reg 1:0 Buf;assignQ, Qn = Buf;always (negedge Set_N or negedge Rst_N or posedge Clk)case(Rst_N,Set_N)0: Buf = 2b11;1: Buf = 2b10;2: Buf = 2b01;default:Buf = D,D;endcaseendmodule/74HC74測試平臺代碼/ test_74.vtimescale 1ns/1nsmodule test_74;reg s, r, clk, d;wire q, qn;HC74 u(s, r, clk, d, q, qn);task clock;repeat(10)begin d = 0; #3;d = 1; #3;endendtaskalwaysbeginclk = 0;#2;clk = 1;#2;endinitialbegin s = 0;r = 1;clock;#5 s = 1;r = 0;clock;#5 s = 0;r = 0;clock;#5 s = 1;r = 1;clock;endendmodule/74HC112代碼/ 74HC112.vmodule HC112(Set_N, Rst_N, Clk_N, J, K, Q, Qn);inputSet_N, Rst_N, Clk_N, J, K;outputQ, Qn;regQ;assign Qn = Q;always (negedge Set_N or negedge Rst_N or negedge Clk_N)case(Set_N,Rst_N) 0: Q = 1; 1: Q = 1; 2: Q = 0; default: case(J,K) 0: Q = Q; 1: Q = 0; 2: Q = 1; default: Q = Q;endcaseendcaseendmodule/74HC112測試平臺代碼/ test_112.vtimescale 1ns/1nsmodule test_112;reg set, res, clk, j, k;wire q, qn;HC112 u(set, res, clk, j, k, q, qn);always#5 clk = clk;task clock;repeat(3)beginj = 0;k = 1;#20; j = 1;k = 0;#20;j = 0;k = 0;#20; j = 1;k = 1;#20;endendtaskinitialbeginclk = 0;set = 0;res = 0;clock;set = 0;res = 1;clock;set = 1;res = 0;clock;set = 1;res = 1;clock;endendmodule/74HC161代碼/ 74HC161.vmodule HC161(CP,CEP,CET,MRN,PEN,Dn,Qn,TC); input CP; input CEP,CET; output 3:0Qn; input MRN,PEN; input 3:0Dn; output TC; reg 3:0qaux; always(posedge CP, negedge MRN) begin if(!MRN) qaux=4b0000; else if(!PEN) qaux=Dn; else if(CEP & CET) qaux=qaux+1; else qaux=qaux; end assign TC=(&qaux)&CET; assign Qn=qaux;endmodule/74HC161測試平臺代碼/ 161testbench.vtimescale 1ns/1nsmodule fre_testbench; reg CP,CEP,CET,MRN; reg LT_N,BI_N,LE; reg 3:0Dn; wire TC; wire 3:0Qn; wire 7:0Seg; initial begin CP=0; CEP=1; CET=1; MRN=0; LT_N=1; BI_N=1; LE=0; #10 MRN=1; end parameter clock_period=20; always #(clock_period/2) CP=CP; initial begin Dn=4b0010; (posedge TC)Dn=4b0100; (posedge TC)Dn=4b1000; (posedge TC)Dn=4b1010; (posedge TC)Dn=4b1110; end frequency fre_test(CP,CEP,CET,MRN,Dn,Seg,LT_N,BI_N,LE,Qn,TC);endmodule /74HC194代碼/ 74HC194.vmodule HC194(DataOut, ParIn, SerIn, Sel, Clk, MR_N);output reg3:0 DataOut;input 3:0 ParIn;input1:0 SerIn, Sel;inputClk, MR_N;always (negedge MR_N or posedge Clk)if(MR_N) DataOut = 0;elsecase(Sel) 2b00: DataOut = DataOut; 2b01:If(SerIn1) DataOut = 1b1,DataOut3:1; else DataOut 1; 2b10:if(SerIn0) DataOut = DataOut2:0,1b1; else DataOut = DataOut1; default:DataOut BIA=BIABA=BAB1XXX0XXXXXX1000XXX1XXXXXX00111XX10XXXXX10000XX01XXXXX001101X100XXXX100000X001XXXX00111011100XXX10000100011XXX0011101110100010101000100001001110111011001000000000010100011111111001010注：X為任意狀態(tài)表4-11 74HC283輸入輸出狀態(tài)進(jìn)位輸入4位加數(shù)輸入4位被加數(shù)輸入輸出加法結(jié)果和進(jìn)位CinA4A3A2A1B4B3B2B1CoutS4S3S2S10000001100011011111111111110001110010010011010001100101010101011101100110000111010011001表4-12 74HC4511輸入輸出狀態(tài)使能輸入數(shù)據(jù)輸入譯碼輸出LEDCBAabcdefg0XXXXXX111111110XXXXX000000011000001111